Freescale Semiconductor MPC8260 11.2 Basic Architecture

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-4 Freescale Semiconductor
— User-specified control-signal patterns run when an internal or external master requests a
single-beat or burst read or write access.
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and 512
Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
– Chip-select line
– Byte- select lines
– Six external general-purpose lines
— Supports 8-, 16-, 32-, and 64-bit memory port sizes, 8-, 16-, and 32-bit port sizes on the local
bus
— Page mode support for successive transfers within a burst
— Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and
512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks
11.2 Basic Architecture
The memory controller consists of three basic machines:
• Synchronous DRAM machine
• General-purpose chip-select machine (GPCM)
• Three UPMs
Each bank can be assigned to any one of these machines via BRx[MS] as shown in Figure 11-2. The MS
and MxMR[BSEL] bits (for UPMs) assign banks to the 60x bus or local bus, as shown in Figure11-2..
Addresses are decoded by comparing (A[0–16] bit-wise and ORx[AM]) with BRx[BA]. If an address
match occurs in multiple banks, the lowest numbered bank has priority. However, if a 60x bus access hits
a bank allocated to the local bus, the access is transferred to the local bus. Local bus access hits to 60x
assigned banks are ignored.
When a memory address matches BRx[BA], the corresponding machine takes ownership of the external
signals that control access and maintains control until the cycle ends.