Freescale Semiconductor MPC8260 11.4.7 SDRAM Interface Timing

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-43
P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory controller to add one cycle for
each SDRAM command. Figure 11-27 illustrates the timing when BUFCMD equals 1.
Figure11-27. BUFCMD = 1
11.4.7 SDRAM Interface Timing
Figure 11-28 through Figure11-36 show SDRAM timing for various types of acce sses.
Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL= 3
CLK
SDAMUX
CMD strobes
MA[0–11] Row Column
Activate Read NOPNOP
(without cs)
CS
ALE
Command setup cycle Command setup cycle
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11] Row Column
WE
DQM
Data D0