Freescale Semiconductor MPC8260 19.10 IDMA Bus Exceptions

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-28 Freescale Semiconductor
In external request mode (ERM=1), the START_IDMA command initializes the channel, but the first data
transfer is performed after external DREQx assertion.
In internal request mode (ERM=0), the START_IDMA command starts the data transfer almost immediately,
with a delay which depends on the CP load.
19.9.2 STOP_IDMA Command
The STOP_IDMA command is issued to stop the tr ansfer of an IDMA channel.
When a STOP_IDMA command is issued, the CP terminates current IDMA tr ansfers and the current BD is
closed (if it was open). If memory is the destination, all data in the IDMA internal buffer is transferred to
memory before termination.
At the end of the stop process, the stop-completed event (SC) is set and a maskable interrupt is generated
to the core. The user should not modify channel parameters until SC = 1. When the channel is stopped, it
does not respond to external requests. If a START_IDMA command is reissued, the next BD in the BD table
is processed (if it is valid).
In external request mode (ERM = 1), STOP_IDMA command processing has priority over a peripheral
asserting DONE.
Note: In memory-to-peripheral, peripheral-to-memory, and fly-by modes, if a STOP_IDMA command is
issued with no data in the internal buffer, the BD is immediately closed and the channel is stopped. In this
case, a peripheral expecting DONE to be asserted is not notified because the last transfer of the buffer (with
BD[DDN or SDN] set) is not performed.
19.10 IDMA Bus Exceptions
Bus exceptions can occur while the IDMA has the bus and is transferring operands. In any computer
system, a hardware failure can cause an error during a bus transaction due to random noise or an illegal
access. When a synchronous bus structure (like those supported by the PowerQUICC II) is used, it is easy
to make provisions for a bus master to detect and respond to errors during a bus transaction. The IDMA
recognizes the same bus exceptions as the core, reset and transfer error, as described in Table19-11.
Table19-11. IDMA Bus Exceptions
Exception Description
Reset On an external reset, the IDMA immediately aborts the channel operation, returns to the idle state, and
clears IDSR. If reset is detected when a bus transaction is in progress, the transaction is terminated, the
control and address/data pins are three-stated, and bus mastership is released.
Transfer
Error
When a fatal error occurs during a bus transaction, a bus error exception is used to abort the transaction
and systematically terminate channel operation. The IDMA terminates the current bus transaction,
signals an error in the SDSR, and signals an interrupt if the corresponding bit in the SDMR is set. The
CPM must be reset before IDMA operation is restarted. Any data previously read from the source into the
internal storage is lost, however, issuing a START_IDMA command transfers the last BD again.
Note: Any source or destination device for an operand under IDMA handshake control for single-address
transfers may need to monitor TEA to detect a bus exception for the current bus transaction. TEA
terminates the transaction immediately and negates DACK, which is used to control the transfer to/from
the device.