Freescale Semiconductor MPC8260 33.3 IMA Microcode Architecture

Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
33-10 Freescale Semiconductor
Figure 33-4. IMA Frame and ICP Cell Formats
The IMA protocol must compensate for potential differences in delay between the different links of the
IMA group. The allowable delay differential for DS1/E1 links is 25ms, which at E1 rates is equivalent to
approximately 118 cells.
33.2.3.2 IMA Filler Cells
At the transmitting end, cells are transmitted continuously. If there are no ATM layer cells to be sent
between ICP cells within an IMA frame, then the IMA transmitter sends filler cells to maintain a
continuous stream of cells at the physical layer. The insertion of Filler cells provides cell rate decoupling
at the IMA sublayer. The Filler cells should be discarded by the IMA receiver.
33.3 IMA Microcode Architecture
This chapter explains the architecture of the receive and transmit IMA microcode tasks.
33.3.1 IMA Function Partitioning
The IMA microcode performs only those functions with regular, critical real-time demands. The other
functions of IMA (e.g. control and management) are the responsibility of host software. As such, the IMA
microcode corresponds primarily to the user plane functions defined in the IMA specification, and
software must provide the layer management and plane management functionality. The IMA microcode
provides interrupts when interaction with layer management and plane management is required.
Cell 1Cell 2
Cell 3
Cell 4
Cell n
IMA Frame
ICP Cell
.....
ICP Cell offset should be different for each link.
ICP cell offset is determined at start-up.
FSN
IMA
Link
ICP
Cell Cell ID
ICP Cell
Header
OAM
Label
PTI/CLP = b1011
HEC = 0x64
Link ID
IMA
cell
offset
SI ID
Stat. &
Ctrl CI
Grp.
Ctrl.
Stat. &
TX
timing
info
TX
test
ctrl
TX
test
ptrn.
RX
test
ptrn
Link
info. Xend to
end
ch.
CRC
1-5 678910 11 12 13 14 15 16 17 18-49 50 51 52-53
Link information for links 0-31