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Texas Instruments TMS320C645x DSP manual

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Contents

Main Page Contents Page Page Page Page Page Page Preface Read This First 1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1.3 Functional Block Diagram Page 2 EMAC Functional Architecture 2.1 Clock Control 2.2 Memory Map 2.3 System Level Connections 2.3.1 Media Independent Interface (MII) Connections Page 2.3.2 Reduced Media Independent Interface (RMII) Connections Page 2.3.3 Gigabit Media Independent Interface (GMII) Connections Page Page Page 2.4 Ethernet Protocol Overview Page 2.5 Programming Interface Page Page Page Page Page Page 2.5.5 Receive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure Format Page Page Page 2.6 EMAC Control Module 2.7 Management Data Input/Output (MDIO) Module Page Page Page Page 2.8 EMAC Module Page Page 2.9 Media Independent Interfaces Page Page Page 2.10 Packet Receive Operation Page Page Page Page 2.11 Packet Transmit Operation 2.12 Receive and Transmit Latency 2.13 Transfer Node Priority 2.14 Reset Considerations 2.15 Initialization Page Page 2.16 Interrupt Support Page Page 2.17 Power Management 2.18 Emulation Considerations 3 EMAC Control Module Registers 3.1 Introduction 3.2 EMAC Control Module Interrupt Control Register (EWCTL) 3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) 4 MDIO Registers 4.1 Introduction 4.2 MDIO Version Register (VERSION) 4.3 MDIO Control Register (CONTROL) Table 16. MDIO Control Register (CONTROL) Field Descriptions 4.4 PHY Acknowledge Status Register (ALIVE) 4.5 PHY Link Status Register (LINK) 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 4.12 MDIO User Access Register 0 (USERACCESS0) Table 25. MDIO User Access Register 0 (USERACCESS0) Field Descriptions 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) Table 26. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions 4.14 MDIO User Access Register 1 (USERACCESS1) Table 27. MDIO User Access Register 1 (USERACCESS1) Field Descriptions 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) Table 28. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions 5 EMAC Port Registers 5.1 Introduction Page Page Page 5.2 Transmit Identification and Version Register (TXIDVER) 5.3 Transmit Control Register (TXCONTROL) 5.4 Transmit Teardown Register (TXTEARDOWN) Table 32. Transmit Teardown Register (TXTEARDOWN) Field Descriptions 5.5 Receive Identification and Version Register (RXIDVER) 5.6 Receive Control Register (RXCONTROL) 5.7 Receive Teardown Register (RXTEARDOWN) Table 35. Receive Teardown Register (RXTEARDOWN) Field Descriptions 5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Table 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions 5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Table 37. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) Table 38. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions 5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Table 39. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions 5.12 MAC Input Vector Register (MACINVECTOR) Table 40. MAC Input Vector Register (MACINVECTOR) Field Descriptions 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Table 41. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Table 42. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) Table 43. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Table 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Page 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) Table 50. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) Table 51. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions 5.24 Receive Maximum Length Register (RXMAXLEN) 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) 5.29 MAC Control Register (MACCONTROL) Table 57. MAC Control Register (MACCONTROL) Field Descriptions Table 57. MAC Control Register (MACCONTROL) Field Descriptions (continued) 5.30 MAC Status Register (MACSTATUS) Table 58. MAC Status Register (MACSTATUS) Field Descriptions Table 58. MAC Status Register (MACSTATUS) Field Descriptions (continued) 5.31 Emulation Control Register (EMCONTROL) 5.32 FIFO Control Register (FIFOCONTROL) 5.33 MAC Configuration Register (MACCONFIG) 5.34 Soft Reset Register (SOFTRESET) 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) 5.37 MAC Hash Address Register 1 (MACHASH1) 5.38 MAC Hash Address Register 2 (MACHASH2) 5.39 Back Off Test Register (BOFFTEST) Table 67. Back Off Test Register (BOFFTEST) Field Descriptions 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) 5.41 Receive Pause Timer Register (RXPAUSE) 5.42 Transmit Pause Timer Register (TXPAUSE) 5.43 MAC Address Low Bytes Register (MACADDRLO) Table 71. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions 5.44 MAC Address High Bytes Register (MACADDRHI) 5.45 MAC Index Register (MACINDEX) 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) 5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) 5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) 5.50 Network Statistics Registers Page Page Page Page Page Page Page Page Appendix A Glossary Page Appendix B Revision History