Texas Instruments TMS320C645x DSP Management Data Input/Output Mdio Module, Interrupt Control

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EMAC Functional Architecture

2.6.3Interrupt Control

The EMAC control module combines the multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller.

The control module uses two registers to control the interrupt signal to the CPU. First, the INTEN bit in the EWCTL register globally enables and disables the interrupt signal to the CPU. The INTEN bit drives the interrupt line low during interrupt processing. Upon re-enabling the bit, the interrupt signal will rise if another interrupt condition exists, creating a rising edge detectable by the CPU.

The EMAC control module interrupt timer count register (EWINTTCNT) is programmed with a value that counts down once the EMAC/MDIO interrupts are enabled using EWCTL. The CPU interrupt signal is prevented from rising again until this count reaches zero.

The EWINTTCNT has no effect on interrupts once the count reaches zero, so there is no induced interrupt latency on random sporadic interrupts. However, the count delays the issuing of a second interrupt immediately after a first. This protects the system from entering interrupt thrashing mode, in which the software interrupt service routine (ISR) completes processing just in time to receive another interrupt. By postponing subsequent interrupts in a back-to-back condition, the software application or driver can perform more work in its ISR. The EWINTTCNT reset value can be adjusted from within the ISR according to current system load, or set to a fixed value that assures a maximum number of interrupts per second.

The counter counts at the peripheral clock frequency of CPU clock/6. The default reset count is 0 (inactive), the maximum value is 1 FFFFh (131 071).

2.7Management Data Input/Output (MDIO) Module

The Management Data Input/Output (MDIO) module manages up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC). The MDIO module allows almost transparent operation of the MDIO interface with little maintenance from the CPU.

The MDIO module enumerates all PHY devices in the system by continuously polling 32 MDIO addresses. Once it detects a PHY device, the MDIO module reads the PHY status register to monitor the PHY link state. The MDIO module stores link change events that can interrupt the CPU. The event storage allows the CPU to poll the link status of the PHY device without continuously performing MDIO module accesses. However, when the system must access the MDIO module for configuration and negotiation, the MDIO module performs the MDIO read or write operation independent of the CPU. This independent operation allows the DSP to poll for completion or interrupt the CPU once the operation has completed.

2.7.1MDIO Module Components

The MDIO module (Figure 12) interfaces to PHY components through two MDIO pins (MDCLK and MDIO), and to the DSP core through the EMAC control module and the configuration bus. The MDIO module consists of the following logical components:

∙MDIO clock generator

∙Global PHY detection and link state monitoring

∙Active PHY monitoring

∙PHY register user access

38 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRU975B –August 2006

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