Texas Instruments TMS320C645x DSP manual Initialization, Enabling the EMAC/MDIO Peripheral

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EMAC Functional Architecture

2.15 Initialization

2.15.1Enabling the EMAC/MDIO Peripheral

When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a value of zero. The interface to be used (MII, RMII, GMII, or RGMII) is automatically selected at power-on reset, based on the state of the MACSEL configuration pins.

EMAC/MDIO is enabled through the chip level module state control register 0 (MDCTL0) and module status register 0 (MDSTAT0). For detailed information on the programming sequence, see the device-specific data manual. This sequence will enable the EMAC peripheral, and the register values are reset to default. Module-specific initialization may proceed.

2.15.2EMAC Control Module Initialization

The EMAC control module is used for global interrupt enable, and to pace back-to-back interrupts using an interrupt re-trigger count based on the peripheral clock (CPUclk/6). There is also an 8K block of RAM local to the EMAC that holds packet buffer descriptors.

Note that although the EMAC control module and the EMAC module have slightly different functions, in practice, the type of maintenance performed on the EMAC control module is more commonly conducted from the EMAC module software (as opposed to the MDIO module).

The initialization of the EMAC control module consists of two parts:

1.Configuration of the interrupt on the DSP.

2.Initialization of the EMAC control module:

–Setting the interrupt pace count (using EWINTTCNT)

–Initializing the EMAC and MDIO modules

–Enabling interrupts in the EMAC control module (using EWCTL)

See Example 4 to view example code used to perform the actions associated with the second part of the EMAC control module initialization when using the register-level CSL.

Use the system’s interrupt controller to map the EMAC interrupts to one of the CPU’s interrupts. Once the interrupt is mapped to a CPU interrupt, general masking and unmasking of the interrupt (to control reentrancy) should be done at the chip level by manipulating the interrupt enable mask. The EMAC control module control register (EWCTL) should only enable and disable interrupts from within the EMAC interrupt service routine (ISR), as disabling and re-enabling the interrupt in EWCTL also resets the interrupt pace counter.

SPRU975B –August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 57

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