Texas Instruments TMS320C645x DSP manual Transfer Node Priority, Reset Considerations

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EMAC Functional Architecture

Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register in the C645x devices. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module.

2.13 Transfer Node Priority

The C645x devices contain a system level priority allocation register (PRI_ALLOC) that sets the priority of the transfer node used in issuing memory transfer requests to system memory.

Although the EMAC has internal FIFOs to help alleviate memory transfer arbitration problems, the average transfer rate of data read and written by the EMAC to internal or external DSP memory must be at least equal to the Ethernet wire rate. In addition, the internal FIFO system can not withstand a single memory latency event greater than the time it takes to fill or empty a TXCELLTHRESH number of internal 64-byte FIFO cells.

For example, for 1000 Mbps operation, these restrictions translate into the following rules:

∙For the short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 0.512 μs.

∙Any single latency event in request servicing can be no longer than (0.512 * TXCELLTHRESH) μs.

Bits [0-2] of the PRI_ALLOC register set the transfer node priority for all the master peripherals in the device, including EMAC. A value of 000b will have the highest priority, while 111b will have the lowest. The default priority assigned to EMAC is 001b. It is important to have a balance between all peripherals. In most cases, the default priorities will not need adjustment.

2.14 Reset Considerations

2.14.1Software Reset Considerations

For information on the chip level reset capabilities of various peripherals, see the device-specific data manual.

Within the peripheral itself, the EMAC component of the Ethernet MAC peripheral can be placed in a reset state by writing to the SOFTRESET register located in EMAC memory map. Writing a one to bit 0 of this register causes the EMAC logic to be reset, and the register values to be set to their default values. Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration bus; it is the responsibility of the software to verify that there are no pending frames to be transferred. After writing a one to this bit, it may be polled to determine if the reset has occurred. A value of one indicates that the reset has not yet occurred. A value of zero indicates that a reset has occurred.

After a software reset operation, all the EMAC registers need to be re-initialized for proper data transmission.

Unlike the EMAC module, the MDIO and EMAC control modules cannot be placed in reset from a register inside their memory map.

2.14.2Hardware Reset Considerations

When a hardware reset occurs, the EMAC peripheral will have its register values reset, and all the sub-modules will return to their default state. After the hardware reset, the EMAC needs to be initialized before resuming its data transmission, as described in Section 2.15.

A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are triggered by errors in packet buffer descriptors. Before doing a hardware reset, you should inspect the error codes in the MACSTATUS register. This register provides information about the software error type that needs correction. For more information on error interrupts, see Section 2.16.1.4.

56 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRU975B –August 2006

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