List of Tables

 

1

Interface Selection Pins

16

 

2

EMAC and MDIO Signals for MII Interface

17

 

3

EMAC and MDIO Signals for RMII Interface

19

 

4

EMAC and MDIO Signals for GMII Interface

21

 

5

EMAC and MDIO Signals for RGMII Interface

23

 

6

Ethernet Frame Description

24

 

7

Basic Descriptors

26

 

8

Receive Frame Treatment Summary

53

 

9

Middle of Frame Overrun Treatment

54

 

10

Emulation Control

63

 

11

EMAC Control Module Registers

64

 

12

EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions

64

 

13

EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions

65

 

14

Management Data Input/Output (MDIO) Registers

66

 

15

MDIO Version Register (VERSION) Field Descriptions

67

 

16

MDIO Control Register (CONTROL) Field Descriptions

68

 

17

PHY Acknowledge Status Register (ALIVE) Field Descriptions

69

 

18

PHY Link Status Register (LINK) Field Descriptions

70

 

19

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions

71

 

20

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions

72

 

21

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions

73

 

22

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions

74

 

23

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions

75

 

24

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field

 

 

 

Descriptions

76

 

25

MDIO User Access Register 0 (USERACCESS0) Field Descriptions

77

 

26

MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions

78

 

27

MDIO User Access Register 1 (USERACCESS1) Field Descriptions

79

 

28

MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions

80

 

29

Ethernet Media Access Controller (EMAC) Registers

81

 

30

Transmit Identification and Version Register (TXIDVER) Field Descriptions

85

 

31

Transmit Control Register (TXCONTROL) Field Descriptions

86

 

32

Transmit Teardown Register (TXTEARDOWN) Field Descriptions

87

 

33

Receive Identification and Version Register (RXIDVER) Field Descriptions

88

 

34

Receive Control Register (RXCONTROL) Field Descriptions

89

 

35

Receive Teardown Register (RXTEARDOWN) Field Descriptions

90

 

36

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions

91

 

37

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions

92

 

38

Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions

93

 

39

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions

94

 

40

MAC Input Vector Register (MACINVECTOR) Field Descriptions

95

 

41

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions

96

 

42

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions

97

 

43

Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions

98

 

44

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions

99

 

45

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions

100

 

46

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions

101

 

47

MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions

102

 

48

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

103

 

49

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions

104

8

List of Tables

SPRU975B –August 2006

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Texas Instruments TMS320C645x DSP manual List of Tables