www.ti.com
EMAC Functional Architecture
2.16.1.4Host Error Interrupt
The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions due to the handling of buffer descriptors detected during transmit or receive DMA transactions. The failure of the software application to supply properly formatted buffer descriptors results in this error. The error bit can only be cleared by resetting the EMAC module in hardware.
The host error interrupt is enabled by setting the HOSTMASK bit in the MACINTMASKSET register. The host error interrupt is disabled by clearing the appropriate bit in the MACINTMASKCLEAR register. The raw and masked host error interrupt status may be read by reading the MACINTSTATRAW and MACINTSTATMASKED registers, respectively.
Transmit host error conditions include:
∙SOP error
∙Ownership bit not set in SOP buffer
∙Zero next buffer descriptor pointer without EOP
∙Zero buffer pointer
∙Zero buffer length
∙Packet length error
Receive host error conditions include:
∙Ownership bit not set in input buffer
∙Zero buffer pointer
2.16.2MDIO Module Interrupt Events and Requests
The MDIO module generates two interrupt events, as follows:
∙LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link.
∙USERINT: Serial interface user command event complete interrupt.
2.16.2.1Link Change Interrupt
The MDIO module asserts a link change interrupt (LINKINT) if there is a change in the link state of the PHY corresponding to the address in the PHYADRMON bits in the USERPHYSELn register, and if the LINKINTENB bit is also set in USERPHYSELn. This interrupt event is also captured in the LINKINTRAW bits of the LINKINTRAW register. The LINKINTRAW bits 0 and 1 correspond to USERPHYSEL0 and USERPHYSEL1, respectively.
When the interrupt is enabled and generated, the corresponding bit is also set in the LINKINTMASKED register. The interrupt is cleared by writing back the same bit to LINKINTMASKED (write to clear).
2.16.2.2User Access Completion Interrupt
A user access completion interrupt (USERINT) is asserted when the GO bit in one of the USERACCESSn registers transitions from 1 to 0 (indicating completion of a user access) and the bit in the USERINTMASKSET register corresponding to USERACCESS0 or USERACCESS1 is set. This interrupt event is also captured in bits 0 and 1 of the USERINTRAW register. USERINTRAW bits 0 and bit 1 correspond to USERACCESS0 and USERACCESS1, respectively.
When the interrupt is enabled and generated, the corresponding USERINTMASKED bit is also set in the USERINTMASKED register. The interrupt is cleared by writing back the same bit to USERINTMASKED (write to clear).
62 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | SPRU975B |
