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Texas Instruments TMS320C645x DSP manual Management Data Input/Output Mdio Registers

Models: TMS320C645x DSP

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MDIO Registers

4 MDIO Registers

4.1Introduction

Table 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See the device-specific data manual for the memory address of these registers.

Table 14. Management Data Input/Output (MDIO) Registers

Offset	Acronym	Register Description	Section
0h	VERSION	MDIO Version Register	Section 4.2
4h	CONTROL	MDIO Control Register	Section 4.3
8h	ALIVE	PHY Alive Status register	Section 4.4
Ch	LINK	PHY Link Status Register	Section 4.5
10h	LINKINTRAW	MDIO Link Status Change Interrupt (Unmasked) Register	Section 4.6
14h	LINKINTMASKED	MDIO Link Status Change Interrupt (Masked) Register	Section 4.7
20h	USERINTRAW	MDIO User Command Complete Interrupt (Unmasked) Register	Section 4.8
24h	USERINTMASKED	MDIO User Command Complete Interrupt (Masked) Register	Section 4.9
28h	USERINTMASKSET	MDIO User Command Complete Interrupt Mask Set Register	Section 4.10
2Ch	USERINTMASKCLEAR	MDIO User Command Complete Interrupt Mask Clear Register	Section 4.11
80h	USERACCESS0	MDIO User Access Register 0	Section 4.12
84h	USERPHYSEL0	MDIO User PHY Select Register 0	Section 4.13
88h	USERACCESS1	MDIO User Access Register 1	Section 4.14
8Ch	USERPHYSEL1	MDIO User PHY Select Register 1	Section 4.15

66	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	SPRU975B –August 2006
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Texas Instruments TMS320C645x DSP manual Management Data Input/Output Mdio Registers

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramIndustry Standards Compliance Statement Rmii Clocking Clock ControlMII Clocking Gmii ClockingMemory Map Rgmii ClockingInterface Selection Pins System Level ConnectionsMedia Independent Interface MII Connections Mrxdv Emac and Mdio Signals for MII InterfaceMtxen ControlReduced Media Independent Interface Rmii Connections Mtxen Mcrsdv MrefclkMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Gigabit Media Independent Interface Gmii Connections Mtclk GmtclkEmac and Mdio Signals for Gmii Interface Signal Name DescriptionTXC Txctl Refclk RXCRxctl Mdclk Mdio Emac and Mdio Signals for Rgmii Interface TXCEthernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Multiple Access Protocol Programming Interface Packet Buffer DescriptorsBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts SOP EOP Owner EOQ Tdown Pass Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format Cmplt CRCBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure FormatNext Descriptor Pointer Jabber Flag Oversize FlagCRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Fragment FlagBus Arbiter Emac Control ModuleInternal Memory CPUManagement Data Input/Output Mdio Module Interrupt ControlMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio ModuleExample of Mdio Register Access Code Writing Data to a PHY RegisterReading Data From a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadrReceive DMA Engine Emac ModuleEmac Module Components Receive FifoTransmit DMA Engine MAC ReceiverReceive Address Transmit FifoClock and Reset Logic Emac Module Operational OverviewReceive Control Media Independent InterfacesData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow ControlAdaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Channel Addressing Hardware Receive QOS SupportHost Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Overrun Middle of Frame Overrun TreatmentReceive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel TeardownHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Transfer Node PriorityInitialization Enabling the EMAC/MDIO PeripheralEmac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Statistics InterruptMdio Module Interrupt Events and Requests Host Error InterruptUser Access Completion Interrupt Link Change InterruptProper Interrupt Processing Power ManagementEmulation Considerations Interrupt MultiplexingIntroduction Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Ewint TcntManagement Data Input/Output Mdio Registers Modid Revmaj Revmin Mdio Version Register VersionMdio Version Register Version Field Descriptions ModidMdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field DescriptionsPHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Userintmask ClearMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers RX7FREEBUFFER MacconfigSoftreset MaccontrolTX6CP RxcrcerrorsRxaligncodeerrors TX7CPRxsofoverruns FRAME1024TUPNetoctets RxmofoverrunsTransmit Identification and Version Register Txidver Txident Txmajorver TxminorverTxident Transmit Control Register Txcontrol Transmit Control Register Txcontrol Field DescriptionsTxen Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Rxident Rxmajorver RxminorverRxident Receive Control Register Rxcontrol Receive Control Register Rxcontrol Field DescriptionsRxen Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw Host Stat PendMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedHostmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchRxbroaden RxbroadchRxmulten RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN Receive Unicast Enable Set Register RxunicastsetRxmultch RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field DescriptionsReceive Buffer Offset Register Rxbufferoffset RxbufferOffset Rxfilterthresh Reserved RX nFLOW ThreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsGIG CmdidleTxptype TxpaceTxerrcode MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions TxerrchRgmiigig RxerrcodeRxerrch RgmiifullSoft Free Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions SoftRxfifoflowthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions TxcellthreshTxcelldepth Rxcelldepth Addresstype Maccfig MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions TxcelldepthSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MACSRCADDR0 MACSRCADDR1MACSRCADDR0 MAC Source Address High Bytes Register Macsrcaddrhi MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5MACSRCADDR2 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field DescriptionsMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsRndnum Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions CollcountTransmit Pacing Algorithm Test Register Tpacetest PacevalReceive Pause Timer Register Rxpause Receive Pause Timer Register Rxpause Field DescriptionsPausetimer Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions ValidMAC Address High Bytes Register Macaddrhi MACADDR2 MACADDR3 MACADDR4 MACADDR5MACADDR2 MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTX nHDP RX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TX nCPReceive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RX nCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersStatistics Register Field Descriptions Broadcast Receive Frames Register RxbcastframesMulticast Receive Frames Register Rxmcastframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesReceive Undersized Frames Register Rxundersized Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Frame Fragments Register RxfragmentsReceive Octet Frames Register Rxoctets Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Good Transmit Frames Register TxgoodframesPause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register TxdeferredTransmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register TxlatecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionAppendix B Revision History Table B-1. Document Revision HistoryImportant Notice