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MDIO Registers
4.7MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 21 and described in Table 20.
Figure 21. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
31 |
| 16 | |
Reserved |
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15 | 2 | 1 | 0 |
Reserved |
| LINKINT |
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| MASKED | |
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LEGEND: R = Read only; R/WC = Read/Write 1 to clear;
Table 20. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field
Descriptions
Bit | Field | Value | Description |
| Reserved | 0 | Reserved |
LINKINTMASKED |
| MDIO Link change interrupt, masked value. . When asserted, a bit indicates that there was an | |
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| MDIO link change event (i.e. change in the LINK register) corresponding to the PHY address in the |
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| USERPHYSEL register and the corresponding LINKINTENB bit was set. LINKINTRAW[0] and |
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| LINKINTRAW[1] correspond to USERPHYSEL0 and USERPHYSEL1, respectively. Writing a 1 will |
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| clear the event and writing 0 has no effect. |
72 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | SPRU975B |