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EMAC Functional Architecture
2.5.3Transmit and Receive EMAC Interrupts
The EMAC processes descriptors in linked list chains (Section 2.5.1), using the linked list queue mechanism (Section 2.5.2).
The EMAC synchronizes the descriptor list processing by using interrupts to the software application. The interrupts are controlled by the application by using the interrupt masks, global interrupt enable, and the completion pointer register (CP). This register is also called interrupt acknowledge register.
As the EMAC supports eight channels for both transmit and receive, there are eight CP registers for both. They are designated as:
∙TXnCP: Transmit Channel n Completion Pointer (Interrupt Acknowledge) Register
∙RXnCP: Receive Channel n Completion Pointer (Interrupt Acknowledge) Register
These registers serve two purposes. When read, they return the pointer to the last descriptor that the EMAC has processed. When written by the software application, the value represents the last descriptor processed by the software application. If these two values do not match, the interrupt is active.
The system configuration determines whether an active interrupt can interrupt the CPU. In general, the global interrupt for EMAC and MDIO must be enabled in the EMAC control module, and it also must be mapped in the DSP interrupt controller and enabled as a CPU interrupt. If the system is configured properly, the interrupt for a specific receive or transmit channel executes under these conditions when the corresponding interrupt is enabled in the EMAC using the RXINTMASKSET or TXINTMASKSET registers.
The current state of the receive or transmit channel interrupt can be examined directly by the software application by reading the RXINTSTATRAW and TXINTSTATRAW registers, whether or not the interrupt is enabled.
Interrupts are acknowledged when the application software updates the value of TXnCP or RXnCP with a value that matches the internal value kept by the EMAC.
This mechanism ensures that the application software never misses an EMAC interrupt, as the interrupt and its acknowledgment are tied directly to the actual buffer descriptors processing.
SPRU975B | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 29 |
