Valid, Matchfilt | Texas Instruments TMS320C645x DSP guide

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EMAC Port Registers

5.43 MAC Address Low Bytes Register (MACADDRLO)

The MAC address low bytes register (MACADDRLO) is shown in Figure 71 and described in Table 71.

Figure 71. MAC Address Low Bytes Register (MACADDRLO)

31			21	20	19	18	16
	Reserved			VALID	MATCH		CHANNEL
					FILT
	R-0			R/W-x	R/W-x		R/W-x
15	8	7					0
	MACADDR0			MACADDR1
	R/W-0				R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 71. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions

Bit	Field	Value	Description
31-21	Reserved	0	Reserved
20	VALID		Address valid bit. This bit should be cleared to zero for unused address RAM locations.
		0	Address location is not valid and will not be used in determining whether or not an incoming packet
			matches or is filtered
		1	Address location is valid and will be used in determining whether or not an incoming packet
			matches or is filtered
19	MATCHFILT		Match or filter bit.
		0	The address will be used (if VALID is set) to determine if the incoming packet address should be
			filtered
		1	The address will be used (if VALID is set) to determine if the incoming packet address is a match
18-16	CHANNEL		Channel bit; determines which receive channel a valid address match will be transferred to. The
			channel is a don'tcare if the MATCHFILT bit is cleared to zero.
15-8	MACADDR0		MAC address lower 8 bits (byte 0)
7-0	MACADDR1		MAC address bits 15-8 (byte 1)

SPRU975B –August 2006	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	129
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Texas Instruments TMS320C645x DSP MAC Address Low Bytes Register Macaddrlo, Valid Match Channel Filt MACADDR0 MACADDR1

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix B Appendix a List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Industry Standards Compliance Statement MII Clocking Clock ControlRmii Clocking Gmii Clocking Rgmii Clocking Memory Map Interface Selection Pins System Level ConnectionsMedia Independent Interface MII Connections Mtxen Emac and Mdio Signals for MII InterfaceMrxdv Control Reduced Media Independent Interface Rmii Connections Mtxen Mcrsdv MrefclkMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Mtclk Gmtclk Gigabit Media Independent Interface Gmii Connections Signal Name Description Emac and Mdio Signals for Gmii Interface TXC Txctl Refclk RXCRxctl Mdclk Mdio TXC Emac and Mdio Signals for Rgmii Interface Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Multiple Access Protocol Programming Interface Packet Buffer DescriptorsBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Descriptor in C Structure Format Transmit Buffer Descriptor FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRC Buffer Pointer Next Descriptor PointerBuffer Offset Buffer Length Ownership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Example 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor Format Next Descriptor Pointer Oversize Flag Jabber Flag Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Fragment Flag Internal Memory Emac Control ModuleBus Arbiter CPU Management Data Input/Output Mdio Module Interrupt ControlMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Initializing the Mdio Module Mdio Module Operational Overview Example of Mdio Register Access Code Writing Data to a PHY RegisterReading Data From a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access Macros Emac Module Components Emac ModuleReceive DMA Engine Receive Fifo Receive Address MAC ReceiverTransmit DMA Engine Transmit Fifo Emac Module Operational Overview Clock and Reset Logic Data Reception Media Independent InterfacesReceive Control Receive Inter-Frame Interval Ieee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control CRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Hardware Receive QOS Support Receive Channel Addressing Host Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive Mode Middle of Frame Overrun Treatment Receive Overrun Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel Teardown Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Transfer Node Priority Initialization Enabling the EMAC/MDIO PeripheralEmac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Statistics Interrupt Receive Packet Completion Interrupts User Access Completion Interrupt Host Error InterruptMdio Module Interrupt Events and Requests Link Change Interrupt Emulation Considerations Power ManagementProper Interrupt Processing Interrupt Multiplexing Introduction Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Tcnt Ewint Management Data Input/Output Mdio Registers Mdio Version Register Version Field Descriptions Mdio Version Register VersionModid Revmaj Revmin Modid Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register Link Field Descriptions PHY Link Status Register Link 31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Clear Userintmask Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Softreset MacconfigRX7FREEBUFFER Maccontrol Rxaligncodeerrors RxcrcerrorsTX6CP TX7CP Netoctets FRAME1024TUPRxsofoverruns Rxmofoverruns Transmit Identification and Version Register Txidver Txident Txmajorver TxminorverTxident Transmit Control Register Txcontrol Transmit Control Register Txcontrol Field DescriptionsTxen Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Rxident Rxmajorver RxminorverRxident Receive Control Register Rxcontrol Receive Control Register Rxcontrol Field DescriptionsRxen Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register Macinvector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Host Stat Pend MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Host Stat Mask MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen Rxpromch Rxbroaden RxbroadchRxmulten Rxmultch Receive Unicast Enable Set Register RxunicastsetRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register Rxbufferoffset RxbufferOffset Rxfilterthresh Thresh Reserved RX nFLOW Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Txptype CmdidleGIG Txpace MAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusTxerrcode Txerrch Rxerrch RxerrcodeRgmiigig Rgmiifull Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolSoft Free Soft Fifo Control Register Fifocontrol Field Descriptions Fifo Control Register FifocontrolRxfifoflowthresh Txcellthresh MAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigTxcelldepth Rxcelldepth Addresstype Maccfig Txcelldepth Soft Reset Register Softreset Field Descriptions Soft Reset Register Softreset MAC Source Address Low Bytes Register Macsrcaddrlo MACSRCADDR0 MACSRCADDR1MACSRCADDR0 MAC Source Address High Bytes Register Macsrcaddrhi MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5MACSRCADDR2 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2 Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestRndnum Collcount Paceval Transmit Pacing Algorithm Test Register Tpacetest Receive Pause Timer Register Rxpause Receive Pause Timer Register Rxpause Field DescriptionsPausetimer Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register Txpause MAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Match Channel Filt MACADDR0 MACADDR1 Valid MAC Address High Bytes Register Macaddrhi MACADDR2 MACADDR3 MACADDR4 MACADDR5MACADDR2 MAC Index Register Macindex Field Descriptions MAC Index Register Macindex TX nHDP RX nHDP Transmit Channel n Completion Pointer Register TX nCP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel n Completion Pointer Register RX nCP Receive Channel 0-7 Completion Pointer Register RXnCP Statistics Register Field Descriptions Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register Rxpauseframes Receive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive QOS Filtered Frames Register Rxqosfiltered Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Term Definition Table A-1. Physical Layer Definitions Table B-1. Document Revision History Appendix B Revision History Important Notice