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Texas Instruments TMS320C645x DSP manual MAC Interrupt Mask Clear Register Macintmaskclear

Models: TMS320C645x DSP

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EMAC Port Registers

5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 48 and described in Table 48.

Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

31			16
	Reserved
	R-0
15	2	1	0
Reserved		HOST	STAT
		MASK	MASK
R-0		R/WC-0	R/WC-0

LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n= value after reset

Table 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

Bit	Field	Value	Description
31-2	Reserved	0	Reserved
1	HOSTMASK		Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0	STATMASK		Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

SPRU975B –August 2006	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	103
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Texas Instruments TMS320C645x DSP manual MAC Interrupt Mask Clear Register Macintmaskclear

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramIndustry Standards Compliance Statement Gmii Clocking Clock ControlMII Clocking Rmii ClockingRgmii Clocking Memory MapSystem Level Connections Interface Selection PinsMedia Independent Interface MII Connections Control Emac and Mdio Signals for MII InterfaceMtxen MrxdvMtxen Mcrsdv Mrefclk Reduced Media Independent Interface Rmii ConnectionsMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Mtclk Gmtclk Gigabit Media Independent Interface Gmii ConnectionsSignal Name Description Emac and Mdio Signals for Gmii InterfaceTxctl Refclk RXC TXCRxctl Mdclk Mdio TXC Emac and Mdio Signals for Rgmii InterfaceEthernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Multiple Access Protocol Packet Buffer Descriptors Programming InterfaceBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Cmplt CRC Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format SOP EOP Owner EOQ Tdown PassBuffer Length Next Descriptor PointerBuffer Pointer Buffer OffsetTeardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ FlagExample 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor FormatNext Descriptor Pointer Oversize Flag Jabber FlagFragment Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror FlagCPU Emac Control ModuleInternal Memory Bus ArbiterInterrupt Control Management Data Input/Output Mdio ModuleMdio Module Components Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State MonitoringInitializing the Mdio Module Mdio Module Operational OverviewWriting Data to a PHY Register Example of Mdio Register Access CodeReading Data From a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access MacrosReceive Fifo Emac ModuleEmac Module Components Receive DMA EngineTransmit Fifo MAC ReceiverReceive Address Transmit DMA EngineEmac Module Operational Overview Clock and Reset LogicReceive Inter-Frame Interval Media Independent InterfacesData Reception Receive ControlIeee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlInterpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APOSpeed, Duplex, and Pause Frame Support Transmit Flow ControlPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Hardware Receive QOS Support Receive Channel AddressingReceive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeMiddle of Frame Overrun Treatment Receive OverrunTransmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit LatencyTransfer Node Priority Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral InitializationEmac Control Module Initialization Mdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Statistics Interrupt Receive Packet Completion InterruptsLink Change Interrupt Host Error InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsInterrupt Multiplexing Power ManagementEmulation Considerations Proper Interrupt ProcessingEmac Control Module Interrupt Control Register Ewctl IntroductionEmac Control Module Registers Tcnt EwintManagement Data Input/Output Mdio Registers Modid Mdio Version Register VersionMdio Version Register Version Field Descriptions Modid Revmaj RevminMdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link Field Descriptions PHY Link Status Register Link31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Clear UserintmaskMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb PhyadrmonMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Maccontrol MacconfigSoftreset RX7FREEBUFFERTX7CP RxcrcerrorsRxaligncodeerrors TX6CPRxmofoverruns FRAME1024TUPNetoctets RxsofoverrunsTxident Txmajorver Txminorver Transmit Identification and Version Register TxidverTxident Transmit Control Register Txcontrol Field Descriptions Transmit Control Register TxcontrolTxen Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxident Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Receive Control Register Rxcontrol Field Descriptions Receive Control Register RxcontrolRxen Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHost Stat Pend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedStatmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask HostmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen RxcafenRxbroadch RxbroadenRxmulten RXCH7EN Receive Unicast Enable Set Register RxunicastsetRxmultch RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenRxbuffer Receive Buffer Offset Register RxbufferoffsetOffset Rxfilterthresh Thresh Reserved RX nFLOWReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolTxpace CmdidleTxptype GIGTxerrch MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions TxerrcodeRgmiifull RxerrcodeRxerrch RgmiigigSoft Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Soft FreeTxcellthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions RxfifoflowthreshTxcelldepth MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Txcelldepth Rxcelldepth Addresstype MaccfigSoft Reset Register Softreset Field Descriptions Soft Reset Register SoftresetMACSRCADDR0 MACSRCADDR1 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2Collcount Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions RndnumPaceval Transmit Pacing Algorithm Test Register TpacetestReceive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpausePausetimer Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register TxpauseValid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Match Channel Filt MACADDR0 MACADDR1MACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMACADDR2 MAC Index Register Macindex Field Descriptions MAC Index Register MacindexTX nHDP RX nHDP Transmit Channel n Completion Pointer Register TX nCP Transmit Channel 0-7 Completion Pointer Register TXnCPReceive Channel n Completion Pointer Register RX nCP Receive Channel 0-7 Completion Pointer Register RXnCPBroadcast Receive Frames Register Rxbcastframes Network Statistics RegistersStatistics Register Field Descriptions Good Receive Frames Register RxgoodframesPause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Multicast Receive Frames Register RxmcastframesReceive Frame Fragments Register Rxfragments Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedGood Transmit Frames Register Txgoodframes Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsDeferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register TxpauseframesTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register TxmulticollTransmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsTable B-1. Document Revision History Appendix B Revision HistoryImportant Notice