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Texas Instruments TMS320C645x DSP manual Ethernet Media Access Controller Emac Registers

Models: TMS320C645x DSP

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EMAC Port Registers

5 EMAC Port Registers

5.1Introduction

Table 29 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). See the device-specific data manual for the memory address of these registers.

Table 29. Ethernet Media Access Controller (EMAC) Registers

Offset	Acronym	Register Description	Section
0h	TXIDVER	Transmit Identification and Version Register	Section 5.2
4h	TXCONTROL	Transmit Control Register	Section 5.3
8h	TXTEARDOWN	Transmit Teardown Register	Section 5.4
10h	RXIDVER	Receive Identification and Version Register	Section 5.5
14h	RXCONTROL	Receive Control Register	Section 5.6
18h	RXTEARDOWN	Receive Teardown Register	Section 5.7
80h	TXINTSTATRAW	Transmit Interrupt Status (Unmasked) Register	Section 5.8
84h	TXINTSTATMASKED	Transmit Interrupt Status (Masked) Register	Section 5.9
88h	TXINTMASKSET	Transmit Interrupt Mask Set Register	Section 5.10
8Ch	TXINTMASKCLEAR	Transmit Interrupt Clear Register	Section 5.11
90h	MACINVECTOR	MAC Input Vector Register	Section 5.12
A0h	RXINTSTATRAW	Receive Interrupt Status (Unmasked) Register	Section 5.13
A4h	RXINTSTATMASKED	Receive Interrupt Status (Masked) Register	Section 5.14
A8h	RXINTMASKSET	Receive Interrupt Mask Set Register	Section 5.15
ACh	RXINTMASKCLEAR	Receive Interrupt Mask Clear Register	Section 5.16
B0h	MACINTSTATRAW	MAC Interrupt Status (Unmasked) Register	Section 5.17
B4h	MACINTSTATMASKED	MAC Interrupt Status (Masked) Register	Section 5.18
B8h	MACINTMASKSET	MAC Interrupt Mask Set Register	Section 5.19
BCh	MACINTMASKCLEAR	MAC Interrupt Mask Clear Register	Section 5.20
100h	RXMBPENABLE	Receive Multicast/Broadcast/Promiscuous Channel Enable	Section 5.21
		Register
104h	RXUNICASTSET	Receive Unicast Enable Set Register	Section 5.22
108h	RXUNICASTCLEAR	Receive Unicast Clear Register	Section 5.23
10Ch	RXMAXLEN	Receive Maximum Length Register	Section 5.24
110h	RXBUFFEROFFSET	Receive Buffer Offset Register	Section 5.25
114h	RXFILTERLOWTHRESH	Receive Filter Low Priority Frame Threshold Register	Section 5.26
120h	RX0FLOWTHRESH	Receive Channel 0 Flow Control Threshold Register	Section 5.27
124h	RX1FLOWTHRESH	Receive Channel 1 Flow Control Threshold Register	Section 5.27
128h	RX2FLOWTHRESH	Receive Channel 2 Flow Control Threshold Register	Section 5.27
12Ch	RX3FLOWTHRESH	Receive Channel 3 Flow Control Threshold Register	Section 5.27
130h	RX4FLOWTHRESH	Receive Channel 4 Flow Control Threshold Register	Section 5.27
134h	RX5FLOWTHRESH	Receive Channel 5 Flow Control Threshold Register	Section 5.27
138h	RX6FLOWTHRESH	Receive Channel 6 Flow Control Threshold Register	Section 5.27
13Ch	RX7FLOWTHRESH	Receive Channel 7 Flow Control Threshold Register	Section 5.27
140h	RX0FREEBUFFER	Receive Channel 0 Free Buffer Count Register	Section 5.28
144h	RX1FREEBUFFER	Receive Channel 1 Free Buffer Count Register	Section 5.28
148h	RX2FREEBUFFER	Receive Channel 2 Free Buffer Count Register	Section 5.28
14Ch	RX3FREEBUFFER	Receive Channel 3 Free Buffer Count Register	Section 5.28
150h	RX4FREEBUFFER	Receive Channel 4 Free Buffer Count Register	Section 5.28
154h	RX5FREEBUFFER	Receive Channel 5 Free Buffer Count Register	Section 5.28
158h	RX6FREEBUFFER	Receive Channel 6 Free Buffer Count Register	Section 5.28
SPRU975B –August 2006		Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)		81
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Texas Instruments TMS320C645x DSP manual Ethernet Media Access Controller Emac Registers

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramIndustry Standards Compliance Statement MII Clocking Clock ControlRmii Clocking Gmii ClockingRgmii Clocking Memory MapInterface Selection Pins System Level ConnectionsMedia Independent Interface MII Connections Mtxen Emac and Mdio Signals for MII InterfaceMrxdv ControlReduced Media Independent Interface Rmii Connections Mtxen Mcrsdv MrefclkMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Mtclk Gmtclk Gigabit Media Independent Interface Gmii ConnectionsSignal Name Description Emac and Mdio Signals for Gmii InterfaceTXC Txctl Refclk RXCRxctl Mdclk Mdio TXC Emac and Mdio Signals for Rgmii InterfaceEthernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Multiple Access Protocol Programming Interface Packet Buffer DescriptorsBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Descriptor in C Structure Format Transmit Buffer Descriptor FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRCBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagExample 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor FormatNext Descriptor Pointer Oversize Flag Jabber FlagAlignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Fragment FlagInternal Memory Emac Control ModuleBus Arbiter CPUManagement Data Input/Output Mdio Module Interrupt ControlMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY MonitoringInitializing the Mdio Module Mdio Module Operational OverviewExample of Mdio Register Access Code Writing Data to a PHY RegisterReading Data From a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access MacrosEmac Module Components Emac ModuleReceive DMA Engine Receive FifoReceive Address MAC ReceiverTransmit DMA Engine Transmit FifoEmac Module Operational Overview Clock and Reset LogicData Reception Media Independent InterfacesReceive Control Receive Inter-Frame IntervalIeee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlCRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementSpeed, Duplex, and Pause Frame Support Transmit Flow ControlReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Hardware Receive QOS Support Receive Channel AddressingHost Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeMiddle of Frame Overrun Treatment Receive OverrunPacket Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Transfer Node PriorityInitialization Enabling the EMAC/MDIO PeripheralEmac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Statistics Interrupt Receive Packet Completion InterruptsUser Access Completion Interrupt Host Error InterruptMdio Module Interrupt Events and Requests Link Change InterruptEmulation Considerations Power ManagementProper Interrupt Processing Interrupt MultiplexingIntroduction Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Tcnt EwintManagement Data Input/Output Mdio Registers Mdio Version Register Version Field Descriptions Mdio Version Register VersionModid Revmaj Revmin ModidMdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link Field Descriptions PHY Link Status Register Link31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Clear UserintmaskMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon LinkselMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Softreset MacconfigRX7FREEBUFFER MaccontrolRxaligncodeerrors RxcrcerrorsTX6CP TX7CPNetoctets FRAME1024TUPRxsofoverruns RxmofoverrunsTransmit Identification and Version Register Txidver Txident Txmajorver TxminorverTxident Transmit Control Register Txcontrol Transmit Control Register Txcontrol Field DescriptionsTxen Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Rxident Rxmajorver RxminorverRxident Receive Control Register Rxcontrol Receive Control Register Rxcontrol Field DescriptionsRxen Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHost Stat Pend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedHost Stat Mask MAC Interrupt Mask Set Register MacintmasksetHostmask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchRxbroaden RxbroadchRxmulten Rxmultch Receive Unicast Enable Set Register RxunicastsetRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset RxbufferOffset Rxfilterthresh Thresh Reserved RX nFLOWReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolTxptype CmdidleGIG TxpaceMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusTxerrcode TxerrchRxerrch RxerrcodeRgmiigig RgmiifullEmulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolSoft Free SoftFifo Control Register Fifocontrol Field Descriptions Fifo Control Register FifocontrolRxfifoflowthresh TxcellthreshMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigTxcelldepth Rxcelldepth Addresstype Maccfig TxcelldepthSoft Reset Register Softreset Field Descriptions Soft Reset Register SoftresetMAC Source Address Low Bytes Register Macsrcaddrlo MACSRCADDR0 MACSRCADDR1MACSRCADDR0 MAC Source Address High Bytes Register Macsrcaddrhi MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5MACSRCADDR2 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestRndnum CollcountPaceval Transmit Pacing Algorithm Test Register TpacetestReceive Pause Timer Register Rxpause Receive Pause Timer Register Rxpause Field DescriptionsPausetimer Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register TxpauseMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Match Channel Filt MACADDR0 MACADDR1 ValidMAC Address High Bytes Register Macaddrhi MACADDR2 MACADDR3 MACADDR4 MACADDR5MACADDR2 MAC Index Register Macindex Field Descriptions MAC Index Register MacindexTX nHDP RX nHDP Transmit Channel n Completion Pointer Register TX nCP Transmit Channel 0-7 Completion Pointer Register TXnCPReceive Channel n Completion Pointer Register RX nCP Receive Channel 0-7 Completion Pointer Register RXnCPStatistics Register Field Descriptions Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register RxpauseframesReceive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsReceive QOS Filtered Frames Register Rxqosfiltered Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesMulticast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsTable B-1. Document Revision History Appendix B Revision HistoryImportant Notice