Texas Instruments TMS320C645x DSP manual Memory Map, Rgmii Clocking

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EMAC Functional Architecture

For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to

GMTCLK.

2.1.4RGMII Clocking

When the RGMII interface is selected by setting MACSEL to 11b, you must configure the internal clock (SYSCLK1) to a 125 MHz frequency by setting the divider for the secondary PLL controller to /5. This provides a reference clock that you can use to source the clock on the RGMII PHY as necessary.

Note: This reference clock is not a free running clock. An external device should only use this clock if it does not expect a valid clock during device reset.

The EMAC drives the transmit clock, while an external PHY generates the receive clock. The reference clock drives the device pin that gives the 125 MHz clock to the PHY; this enables the PHY to generate the receive clock that is sent to EMAC.

The RGMII protocol takes a GMII data stream and turns it into an interface with half of the data bus width and sends the same amount of data with a reduced pinout. The RGMII protocol also allows for dynamic switching of the mode between 10/100/1000 Mbps modes. This negotiation data is embedded in the incoming data stream from the external PHY. For timing purposes, data is transmitted and received with respect to MTCLK and MRCLK respectively.

The RGMII interface has separate I/O pins from the other EMAC pins because the interface voltage is different from the other interfaces.

2.2Memory Map

The EMAC includes an internal memory that holds information about the ethernet packets that are received or transmitted. This internal RAM is 2K x 32 bits in size. You can write data to and read data from the EMAC internal memory via either the EMAC or the CPU. It is used to store buffer descriptors that are 4 words (16 bytes) deep. This 8K local memory can hold enough information to transfer up to 512 ethernet packets without CPU intervention.

You can put the packet buffer descriptors in internal processor memory (L2) on the C645x devices. There are some trade-offs in terms of cache performance and throughput when you put descriptors in L2 versus when you put them in EMAC’s internal memory. Cache performance improves when you put the buffer descriptors in internal memory. However, the EMAC throughput is better when you put the descriptors in the local EMAC RAM.

SPRU975B –August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 15

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