List of Figures
| 1 | EMAC and MDIO Block Diagram | 12 | |
| 2 | Ethernet Configuration with MII Interface | 16 | |
| 3 | Ethernet Configuration with RMII Interface | 18 | |
| 4 | Ethernet Configuration with GMII Interface | 20 | |
| 5 | Ethernet Configuration with RGMII Interface | 22 | |
| 6 | Ethernet Frame | 24 | |
| 7 | Basic Descriptor Format | 26 | |
| 8 | Typical Descriptor Linked List | 27 | |
| 9 | Transmit Descriptor Format | 30 | |
| 10 | Receive Descriptor Format | 33 | |
| 11 | EMAC Control Module Block Diagram | 37 | |
| 12 | MDIO Module Block Diagram | 39 | |
| 13 | EMAC Module Block Diagram | 43 | |
| 14 | EMAC Control Module Interrupt Control Register (EWCTL) | 64 | |
| 15 | EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) | 65 | |
| 16 | MDIO Version Register (VERSION) | 67 | |
| 17 | MDIO Control Register (CONTROL) | 68 | |
| 18 | PHY Acknowledge Status Register (ALIVE) | 69 | |
| 19 | PHY Link Status Register (LINK) | 70 | |
| 20 | MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) | 71 | |
| 21 | MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) | 72 | |
| 22 | MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) | 73 | |
| 23 | MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) | 74 | |
| 24 | MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) | 75 | |
| 25 | MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) | 76 | |
| 26 | MDIO User Access Register 0 (USERACCESS0) | 77 | |
| 27 | MDIO User PHY Select Register 0 (USERPHYSEL0) | 78 | |
| 28 | MDIO User Access Register 1 (USERACCESS1) | 79 | |
| 29 | MDIO User PHY Select Register 1 (USERPHYSEL1) | 80 | |
| 30 | Transmit Identification and Version Register (TXIDVER) | 85 | |
| 31 | Transmit Control Register (TXCONTROL) | 86 | |
| 32 | Transmit Teardown Register (TXTEARDOWN) | 87 | |
| 33 | Receive Identification and Version Register (RXIDVER) | 88 | |
| 34 | Receive Control Register (RXCONTROL) | 89 | |
| 35 | Receive Teardown Register (RXTEARDOWN) | 90 | |
| 36 | Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) | 91 | |
| 37 | Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) | 92 | |
| 38 | Transmit Interrupt Mask Set Register (TXINTMASKSET) | 93 | |
| 39 | Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) | 94 | |
| 40 | MAC Input Vector Register (MACINVECTOR) | 95 | |
| 41 | Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) | 96 | |
| 42 | Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) | 97 | |
| 43 | Receive Interrupt Mask Set Register (RXINTMASKSET) | 98 | |
| 44 | Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) | 99 | |
| 45 | MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) | 100 | |
| 46 | MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) | 101 | |
| 47 | MAC Interrupt Mask Set Register (MACINTMASKSET) | 102 | |
| 48 | MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) | 103 | |
| 49 | Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) | 104 | |
| 50 | Receive Unicast Enable Set Register (RXUNICASTSET) | 106 | |
| 51 | Receive Unicast Clear Register (RXUNICASTCLEAR) | 107 | |
| 52 | Receive Maximum Length Register (RXMAXLEN) | 108 | |
6 | List of Figures | SPRU975B | ||
