Texas Instruments TMS320C645x DSP manual Packet Transmit Operation, Receive and Transmit Latency

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EMAC Functional Architecture

2.11 Packet Transmit Operation

The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round robin as selected by the TXPTYPE bit in the MACCONTROL register. If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round robin priority proceeds from channel 0 to channel 7.

2.11.1Transmit DMA Host Configuration

To configure the transmit DMA for operation, the host must perform the following:

∙Write the MACSRCADDRLO and MACSRCADDRHI registers (used for pause frames on transmit).

∙Initialize the TXnHDP registers to zero.

∙Enable the desired transmit interrupts using the TXINTMASKSET and TXINTMASKCLEAR registers.

∙Set the appropriate configuration bits in the MACCONTROL register.

∙Set up the transmit channel(s) buffer descriptors in host memory.

∙Enable the transmit DMA controller by setting the TXEN bit in the TXCONTROL register.

∙Write the appropriate TXnHDP registers with the pointer to the first descriptor to start transmit operations.

2.11.2Transmit Channel Teardown

The host commands a transmit channel teardown by writing the channel number to the TXTEARDOWN register. When a teardown command is issued to an enabled transmit channel, the following occurs:

∙Any frame currently in transmission completes normally.

∙The TDOWNCMPLT flag is set in the next SOP buffer descriptor in the chain, if there is one.

∙The channel head descriptor pointer is cleared.

∙A transmit interrupt is issued, informing the host of the channel teardown.

∙The corresponding TXnCP register contains the value FFFF FFFCh.

∙The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value. Channel teardown may be commanded on any channel at any time. The host is informed of the teardown completion by the set teardown complete buffer descriptor bit (TDOWNCMPLT). The EMAC does not clear any channel enables due to a teardown command. A teardown command to an inactive channel issues an interrupt that software should acknowledge with an FFFF FFFCh acknowledge value to TXnCP (note that there is no buffer descriptor). Software may read the interrupt acknowledge location (TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh if the interrupt was due to a teardown command.

2.12Receive and Transmit Latency

The transmit FIFO contains twenty four 64-byte cells, and the receive FIFO contains sixty eight 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH cells (configurable through the FIFOCONTROL register) or a complete packet are available in the FIFO.

Transmit under-run cannot occur for packet sizes of TXCELLTHRESH times 64 bytes (or less). For larger packet sizes, transmit under-run can occur if the memory latency is greater than the time required to transmit a 64-byte cell on the wire; this is 0.512 μs in 1 Gbit mode, 5.12 μs in 100 Mbps mode, and 51.2 μs in 10 Mbps mode. The memory latency time includes all buffer descriptor reads for the entire cell data.

The EMAC transmit FIFO uses 24 cells; thus, under-run cannot happen for a normal size packet (less than 1536 packet bytes). Cell transmission can be configured to start only after an entire packet is contained in the FIFO; for a maximum-size packet, set the TXCELLTHRESH field to the maximum possible value of 24.

Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 μs in 1 Gbps mode, 5.12 μs in 100 Mbps mode, or 51.2μs in 10 Mbps mode). The latency time includes any required buffer descriptor reads for the cell data.

SPRU975B –August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 55

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