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Texas Instruments TMS320C645x DSP manual Transmit Pause Timer Register Txpause

Models: TMS320C645x DSP

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EMAC Port Registers

5.42 Transmit Pause Timer Register (TXPAUSE)

The Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70 and described in Table 70.

	Figure 70. Transmit Pause Timer Register (TXPAUSE)
31	16
	Reserved
	R-0
15	0

PAUSETIMER

R-0

LEGEND: R = Read only; -n= value after reset

Table 70. Transmit Pause Timer Register (TXPAUSE) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15-0	PAUSETIMER		Transmit pause timer value. These bits allow the contents of the transmit pause timer to be
			observed. The transmit pause timer is loaded by a received (incoming) pause frame, and then
			decremented at slot time intervals down to 0 at which time EMAC transmit frames are again
			enabled.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRU975B –August 2006

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Texas Instruments TMS320C645x DSP manual Transmit Pause Timer Register Txpause

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramIndustry Standards Compliance Statement Clock Control MII ClockingRmii Clocking Gmii ClockingMemory Map Rgmii ClockingMedia Independent Interface MII Connections Interface Selection PinsSystem Level Connections Emac and Mdio Signals for MII Interface MtxenMrxdv ControlMrxer Mdclk Mdio Reduced Media Independent Interface Rmii ConnectionsMtxen Mcrsdv Mrefclk Emac and Mdio Signals for Rmii Interface Gigabit Media Independent Interface Gmii Connections Mtclk GmtclkEmac and Mdio Signals for Gmii Interface Signal Name DescriptionRxctl Mdclk Mdio TXCTxctl Refclk RXC Emac and Mdio Signals for Rgmii Interface TXCEthernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Multiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Descriptor in C Structure FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRCNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure FormatNext Descriptor Pointer Jabber Flag Oversize FlagCode Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Fragment FlagEmac Control Module Internal MemoryBus Arbiter CPUMdio Module Components Management Data Input/Output Mdio ModuleInterrupt Control PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadrEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoMAC Receiver Receive AddressTransmit DMA Engine Transmit FifoClock and Reset Logic Emac Module Operational OverviewMedia Independent Interfaces Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Channel Addressing Hardware Receive QOS SupportReceive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Overrun Middle of Frame Overrun TreatmentTransmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsHardware Reset Considerations Transfer Node PriorityEmac Control Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Example 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion Interrupts Statistics InterruptHost Error Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change InterruptPower Management Emulation ConsiderationsProper Interrupt Processing Interrupt MultiplexingEmac Control Module Registers IntroductionEmac Control Module Interrupt Control Register Ewctl Ewint TcntManagement Data Input/Output Mdio Registers Mdio Version Register Version Mdio Version Register Version Field DescriptionsModid Revmaj Revmin ModidMdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field DescriptionsPHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Userintmask ClearMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Macconfig SoftresetRX7FREEBUFFER MaccontrolRxcrcerrors RxaligncodeerrorsTX6CP TX7CPFRAME1024TUP NetoctetsRxsofoverruns RxmofoverrunsTxident Transmit Identification and Version Register TxidverTxident Txmajorver Txminorver Txen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Rxident Receive Identification and Version Register RxidverRxident Rxmajorver Rxminorver Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw Host Stat PendMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedMAC Interrupt Mask Set Register Macintmaskset Host Stat MaskHostmask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchRxmulten RxbroadenRxbroadch Receive Unicast Enable Set Register Rxunicastset RxmultchRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field DescriptionsOffset Receive Buffer Offset Register RxbufferoffsetRxbuffer Rxfilterthresh Reserved RX nFLOW ThreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsCmdidle TxptypeGIG TxpaceMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsTxerrcode TxerrchRxerrcode RxerrchRgmiigig RgmiifullEmulation Control Register Emcontrol Emulation Control Register Emcontrol Field DescriptionsSoft Free SoftFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsRxfifoflowthresh TxcellthreshMAC Configuration Register Macconfig MAC Configuration Register Macconfig Field DescriptionsTxcelldepth Rxcelldepth Addresstype Maccfig TxcelldepthSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field DescriptionsMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Back Off Test Register Bofftest Field DescriptionsRndnum CollcountTransmit Pacing Algorithm Test Register Tpacetest PacevalPausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 ValidMACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTX nHDP RX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TX nCPReceive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RX nCPNetwork Statistics Registers Statistics Register Field DescriptionsGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register RxpauseframesReceive Oversized Frames Register Rxoversized Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsFiltered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesBroadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 144 Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionAppendix B Revision History Table B-1. Document Revision HistoryImportant Notice

5.42 Transmit Pause Timer Register (TXPAUSE)

Figure 70. Transmit Pause Timer Register (TXPAUSE)

PAUSETIMER

Table 70. Transmit Pause Timer Register (TXPAUSE) Field Descriptions

PAUSETIMER

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