Texas Instruments TMS320C645x DSP Interrupt Support, Emac Module Interrupt Events and Requests

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EMAC Functional Architecture

2.16 Interrupt Support

2.16.1EMAC Module Interrupt Events and Requests

The EMAC/MDIO generates 18 interrupt events, as follows:

∙TXPENDn: Transmit packet completion interrupt for transmit channels 7 through 0

∙RXPENDn: Receive packet completion interrupt for receive channels 7 through 0

∙STATPEND: Statistics interrupt

∙HOSTPEND: Host error interrupt

2.16.1.1Transmit Packet Completion Interrupts

The transmit DMA engine has eight channels, and each channel has a corresponding interrupt (TXPENDn). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU.

Each of the eight transmit channel interrupts may be individually enabled by setting the appropriate bit in the TXINTMASKSET register. Each of the eight transmit channel interrupts may be individually disabled by clearing the appropriate bit in the TXINTMASKCLEAR register. The raw and masked transmit interrupt status may be read by reading the TXINTSTATRAW and TXINTSTATMASKED registers, respectively.

When the EMAC completes the transmission of a packet, the EMAC issues an interrupt to the CPU by writing the packet’s last buffer descriptor address to the appropriate channel queue’s TX completion pointer located in the state RAM block. The write generates the interrupt when enabled by the interrupt mask, regardless of the value written.

Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges an interrupt by writing the address of the last buffer descriptor processed to the queue’s associated TX completion pointer in the transmit DMA state RAM.

The data written by the host (buffer descriptor address of the last processed buffer) is compared to the data in the register written by the EMAC port (address of last buffer descriptor used by the EMAC). If the two values are not equal, indicating that the EMAC has transmitted more packets than the CPU has processed interrupts for, then the transmit packet completion interrupt signal remains asserted. If the two values are equal, indicating that the host has processed all packets that the EMAC has transferred, then the pending interrupt is cleared. Reading the TXnCP register displays the value that the EMAC is expecting.

The EMAC write to the completion pointer stores the value in the state RAM. The CPU written value does not change the register value. The host-written value is compared to the register content, which was written by the EMAC. If the two values are equal, then the interrupt is removed; otherwise the interrupt remains asserted. The host may process multiple packets prior to acknowledging an interrupt, or the host may acknowledge interrupts for every packet.

60 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRU975B –August 2006

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