Texas Instruments TMS320C645x DSP specs

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EMAC Port Registers

5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)

The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 43 and described in Table 43.

Figure 43. Receive Interrupt Mask Set Register (RXINTMASKSET)

31									16
			Reserved
			R-0
15	8	7	6	5	4	3	2	1	0
Reserved		RX7	RX6	RX5	RX4	RX3	RX2	RX1	RX0
		MASK	MASK	MASK	MASK	MASK	MASK	MASK	MASK
R-0		R/WS-0	R/WS-0	R/WS-0	R/WS-0	R/WS-0	R/WS-0	R/WS-0	R/WS-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 43. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions

Bit	Field	Value	Description
31-8	Reserved	0	Reserved
7	RX7MASK		Receive channel 7 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
6	RX6MASK		Receive channel 6 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
5	RX5MASK		Receive channel 5 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
4	RX4MASK		Receive channel 4 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
3	RX3MASK		Receive channel 3 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
2	RX2MASK		Receive channel 2 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
1	RX1MASK		Receive channel 1 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0	RX0MASK		Receive channel 0 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.

98	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	SPRU975B –August 2006
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Texas Instruments TMS320C645x DSP manual Receive Interrupt Mask Set Register Rxintmaskset

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix a Appendix B List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Industry Standards Compliance Statement Rmii Clocking Clock ControlMII Clocking Gmii Clocking Memory Map Rgmii Clocking Media Independent Interface MII Connections Interface Selection PinsSystem Level Connections Mrxdv Emac and Mdio Signals for MII InterfaceMtxen Control Mrxer Mdclk Mdio Reduced Media Independent Interface Rmii ConnectionsMtxen Mcrsdv Mrefclk Emac and Mdio Signals for Rmii Interface Gigabit Media Independent Interface Gmii Connections Mtclk Gmtclk Emac and Mdio Signals for Gmii Interface Signal Name Description Rxctl Mdclk Mdio TXCTxctl Refclk RXC Emac and Mdio Signals for Rgmii Interface TXC Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Multiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts SOP EOP Owner EOQ Tdown Pass Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format Cmplt CRC Buffer Offset Next Descriptor PointerBuffer Pointer Buffer Length End of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure Format Next Descriptor Pointer Jabber Flag Oversize Flag CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Fragment Flag Bus Arbiter Emac Control ModuleInternal Memory CPU Mdio Module Components Management Data Input/Output Mdio ModuleInterrupt Control Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY Monitoring Mdio Module Operational Overview Initializing the Mdio Module Reading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadr Receive DMA Engine Emac ModuleEmac Module Components Receive Fifo Transmit DMA Engine MAC ReceiverReceive Address Transmit Fifo Clock and Reset Logic Emac Module Operational Overview Receive Control Media Independent InterfacesData Reception Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow Control Adaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Channel Addressing Hardware Receive QOS Support Receive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Promiscuous Receive Mode Receive Frame Treatment Summary Receive Overrun Middle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel Teardown Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Transfer Node Priority Emac Control Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Example 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion Interrupts Statistics Interrupt Mdio Module Interrupt Events and Requests Host Error InterruptUser Access Completion Interrupt Link Change Interrupt Proper Interrupt Processing Power ManagementEmulation Considerations Interrupt Multiplexing Emac Control Module Registers IntroductionEmac Control Module Interrupt Control Register Ewctl Ewint Tcnt Management Data Input/Output Mdio Registers Modid Revmaj Revmin Mdio Version Register VersionMdio Version Register Version Field Descriptions Modid Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link PHY Link Status Register Link Field Descriptions 31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Userintmask Clear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Phyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers RX7FREEBUFFER MacconfigSoftreset Maccontrol TX6CP RxcrcerrorsRxaligncodeerrors TX7CP Rxsofoverruns FRAME1024TUPNetoctets Rxmofoverruns Txident Transmit Identification and Version Register TxidverTxident Txmajorver Txminorver Txen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Rxident Receive Identification and Version Register RxidverRxident Rxmajorver Rxminorver Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field Descriptions Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw Host Stat Pend MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Hostmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask Statmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen Rxpromch Rxmulten RxbroadenRxbroadch RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN Receive Unicast Enable Set Register RxunicastsetRxmultch RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field Descriptions Offset Receive Buffer Offset Register RxbufferoffsetRxbuffer Rxfilterthresh Reserved RX nFLOW Thresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions GIG CmdidleTxptype Txpace Txerrcode MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions Txerrch Rgmiigig RxerrcodeRxerrch Rgmiifull Soft Free Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Soft Rxfifoflowthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions Txcellthresh Txcelldepth Rxcelldepth Addresstype Maccfig MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Txcelldepth Soft Reset Register Softreset Soft Reset Register Softreset Field Descriptions MACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field Descriptions Rndnum Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Collcount Transmit Pacing Algorithm Test Register Tpacetest Paceval Pausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field Descriptions Valid Match Channel Filt MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid MACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex MAC Index Register Macindex Field Descriptions TX nHDP RX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TX nCP Receive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RX nCP Good Receive Frames Register Rxgoodframes Network Statistics RegistersStatistics Register Field Descriptions Broadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register Rxpauseframes Receive Undersized Frames Register Rxundersized Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Frame Fragments Register Rxfragments Receive Octet Frames Register Rxoctets Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Good Transmit Frames Register Txgoodframes Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register Txdeferred Transmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register Txlatecoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 144 Appendix a Glossary Table A-1. Physical Layer Definitions Term Definition Appendix B Revision History Table B-1. Document Revision History Important Notice