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EMAC Functional Architecture
2.15.4EMAC Module Initialization
The EMAC module sends and receives data packets over the network by maintaining up to 8 transmit and receive descriptor queues. The EMAC module configuration must also be kept current based on the PHY negotiation results returned from the MDIO module. Programming this module is the most
A device drive should follow this initialization procedure to get the EMAC to the state where it is ready to receive and send Ethernet packets. Some of these steps are not necessary when performed immediately after device reset.
1.If enabled, clear the device interrupt enable in EWCTL.
2.Clear the MACCONTROL, RXCONTROL, and TXCONTROL registers (not necessary immediately after reset).
3.Initialize all 16 Head Descriptor Pointer registers (RXnHDP and TXnHDP) to 0.
4.Clear all 36 statistics registers by writing 0 (not necessary immediately after reset).
5.Initialize all 32 receive address RAM locations to 0. Set up the addresses to be matched to the eight receive channels and the addresses to be filtered, through programming the MACINDEX, MACADDRHI, and MACADDRLO registers.
6.Initialize the RXnFREEBUFFER, RXnFLOWTHRESH, and RXFILTERLOWTHRESH registers, if buffer flow control is to be enabled. Program the FIFOCONTROL register is FIFO flow control is desired.
7.Most device drivers open with no multicast addresses, so clear the MACHASH1 and MACHASH2 registers.
8.Write the RXBUFFEROFFSET register value (typically zero).
9.Initially clear all unicast channels by writing FFh to the RXUNICASTCLEAR register. If unicast is desired, it can be enabled now by writing the RXUNICASTSET register. Some drivers will default to unicast on device open while others will not.
10.If you desire to transfer jumbo frames, set the RXMAXLEN register to the maximum frame length you want to allow to be received.
11.Set up the RXMBPENABLE register with an initial configuration. The configuration is based on the current receive filter settings of the device driver. Some drivers may enable things like broadcast and multicast packets immediately, while others may not.
12.Set the appropriate configuration bits in the MACCONTROL register (do not set the GMIIEN bit yet).
13.Clear all unused channel interrupt bits by writing RXINTMASKCLEAR and TXINTMASKCLEAR.
14.Enable the receive and transmit channel interrupt bits in RXINTMASKSET and TXINTMASKSET for the channels to be used, and enable the HOSTMASK and STATMASK bits using the MACINTMASKSET register.
15.Initialize the receive and transmit descriptor list queues using the 8K descriptor memory block contained in the EMAC control module.
16.Prepare receive by writing a pointer to the head of the receive buffer descriptor list to RXnHDP.
17.Enable the receive and transmit DMA controllers by setting the RXEN bit in the RXCONTROL register and the TXEN bit in the TXCONTROL register. Then set the GMIIEN bit in MACCONTROL.
18.If the gigabit mode is desired (available only if using GMII or RGMII interface), set the GIG bit in the MACCONTROL register.
19.When using RMII, release the interface logic from reset by clearing the RMII_RST field of the EMAC Configuration register (EMACCFG), found at device level.
20.Enable the device interrupt in EWCTL.
SPRU975B | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 59 |
