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Texas Instruments TMS320C645x DSP manual MAC Interrupt Status Masked Register Macintstatmasked

Models: TMS320C645x DSP

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EMAC Port Registers

5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 46 and described in Table 46.

Figure 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

31			16
Reserved
R-0
15	2	1	0
Reserved		HOST	STAT
		PEND	PEND
R-0		R-0	R-0

LEGEND: R/W = R = Read only; -n= value after reset

Table 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions

Bit	Field	Value	Description
31-2	Reserved	0	Reserved
1	HOSTPEND		Host pending interrupt (HOSTPEND); masked interrupt read
0	STATPEND		Statistics pending interrupt (STATPEND); masked interrupt read

SPRU975B –August 2006	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	101
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Texas Instruments TMS320C645x DSP manual MAC Interrupt Status Masked Register Macintstatmasked

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramIndustry Standards Compliance Statement MII Clocking Clock ControlRmii Clocking Gmii ClockingRgmii Clocking Memory MapMedia Independent Interface MII Connections Interface Selection PinsSystem Level Connections Mtxen Emac and Mdio Signals for MII InterfaceMrxdv ControlMrxer Mdclk Mdio Reduced Media Independent Interface Rmii ConnectionsMtxen Mcrsdv Mrefclk Emac and Mdio Signals for Rmii Interface Mtclk Gmtclk Gigabit Media Independent Interface Gmii ConnectionsSignal Name Description Emac and Mdio Signals for Gmii InterfaceRxctl Mdclk Mdio TXCTxctl Refclk RXC TXC Emac and Mdio Signals for Rgmii InterfaceEthernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Multiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Descriptor in C Structure Format Transmit Buffer Descriptor FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRCBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagExample 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor FormatNext Descriptor Pointer Oversize Flag Jabber FlagAlignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Fragment FlagInternal Memory Emac Control ModuleBus Arbiter CPUMdio Module Components Management Data Input/Output Mdio ModuleInterrupt Control Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY MonitoringInitializing the Mdio Module Mdio Module Operational OverviewReading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access MacrosEmac Module Components Emac ModuleReceive DMA Engine Receive FifoReceive Address MAC ReceiverTransmit DMA Engine Transmit FifoEmac Module Operational Overview Clock and Reset LogicData Reception Media Independent InterfacesReceive Control Receive Inter-Frame IntervalIeee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlCRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementSpeed, Duplex, and Pause Frame Support Transmit Flow ControlReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Hardware Receive QOS Support Receive Channel AddressingReceive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Receive Frame Treatment Summary Promiscuous Receive ModeMiddle of Frame Overrun Treatment Receive OverrunPacket Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Transfer Node PriorityEmac Control Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Example 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Statistics Interrupt Receive Packet Completion InterruptsUser Access Completion Interrupt Host Error InterruptMdio Module Interrupt Events and Requests Link Change InterruptEmulation Considerations Power ManagementProper Interrupt Processing Interrupt MultiplexingEmac Control Module Registers IntroductionEmac Control Module Interrupt Control Register Ewctl Tcnt EwintManagement Data Input/Output Mdio Registers Mdio Version Register Version Field Descriptions Mdio Version Register VersionModid Revmaj Revmin ModidMdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link Field Descriptions PHY Link Status Register Link31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Clear UserintmaskMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon LinkselMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Softreset MacconfigRX7FREEBUFFER MaccontrolRxaligncodeerrors RxcrcerrorsTX6CP TX7CPNetoctets FRAME1024TUPRxsofoverruns RxmofoverrunsTxident Transmit Identification and Version Register TxidverTxident Txmajorver Txminorver Txen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Rxident Receive Identification and Version Register RxidverRxident Rxmajorver Rxminorver Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHost Stat Pend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedHost Stat Mask MAC Interrupt Mask Set Register MacintmasksetHostmask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchRxmulten RxbroadenRxbroadch Rxmultch Receive Unicast Enable Set Register RxunicastsetRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenOffset Receive Buffer Offset Register RxbufferoffsetRxbuffer Rxfilterthresh Thresh Reserved RX nFLOWReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolTxptype CmdidleGIG TxpaceMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusTxerrcode TxerrchRxerrch RxerrcodeRgmiigig RgmiifullEmulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolSoft Free SoftFifo Control Register Fifocontrol Field Descriptions Fifo Control Register FifocontrolRxfifoflowthresh TxcellthreshMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigTxcelldepth Rxcelldepth Addresstype Maccfig TxcelldepthSoft Reset Register Softreset Field Descriptions Soft Reset Register SoftresetMACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestRndnum CollcountPaceval Transmit Pacing Algorithm Test Register TpacetestPausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register TxpauseMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Match Channel Filt MACADDR0 MACADDR1 ValidMACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex Field Descriptions MAC Index Register MacindexTX nHDP RX nHDP Transmit Channel n Completion Pointer Register TX nCP Transmit Channel 0-7 Completion Pointer Register TXnCPReceive Channel n Completion Pointer Register RX nCP Receive Channel 0-7 Completion Pointer Register RXnCPStatistics Register Field Descriptions Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register RxpauseframesReceive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsReceive QOS Filtered Frames Register Rxqosfiltered Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesMulticast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 144 Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsTable B-1. Document Revision History Appendix B Revision HistoryImportant Notice