Texas Instruments TMS320C645x DSP guide

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EMAC Port Registers

5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 44 and described in Table 44.

Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

31									16
			Reserved
			R-0
15	8	7	6	5	4	3	2	1	0
Reserved		RX7	RX6	RX5	RX4	RX3	RX2	RX1	RX0
		MASK	MASK	MASK	MASK	MASK	MASK	MASK	MASK
R-0		R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0

LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n= value after reset

Table 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions

Bit	Field	Value	Description
31-8	Reserved	0	Reserved
7	RX7MASK		Receive channel 7 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
6	RX6MASK		Receive channel 6 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
5	RX5MASK		Receive channel 5 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
4	RX4MASK		Receive channel 4 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
3	RX3MASK		Receive channel 3 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
2	RX2MASK		Receive channel 2 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
1	RX1MASK		Receive channel 1 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0	RX0MASK		Receive channel 0 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

SPRU975B –August 2006	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	99
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Texas Instruments TMS320C645x DSP manual Receive Interrupt Mask Clear Register Rxintmaskclear

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix B Appendix a List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Industry Standards Compliance Statement Gmii Clocking Clock ControlMII Clocking Rmii Clocking Rgmii Clocking Memory Map Interface Selection Pins System Level ConnectionsMedia Independent Interface MII Connections Control Emac and Mdio Signals for MII InterfaceMtxen Mrxdv Reduced Media Independent Interface Rmii Connections Mtxen Mcrsdv MrefclkMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Mtclk Gmtclk Gigabit Media Independent Interface Gmii Connections Signal Name Description Emac and Mdio Signals for Gmii Interface TXC Txctl Refclk RXCRxctl Mdclk Mdio TXC Emac and Mdio Signals for Rgmii Interface Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Multiple Access Protocol Programming Interface Packet Buffer DescriptorsBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Cmplt CRC Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format SOP EOP Owner EOQ Tdown Pass Buffer Length Next Descriptor PointerBuffer Pointer Buffer Offset Teardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ Flag Example 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor Format Next Descriptor Pointer Oversize Flag Jabber Flag Fragment Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror Flag CPU Emac Control ModuleInternal Memory Bus Arbiter Management Data Input/Output Mdio Module Interrupt ControlMdio Module Components Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State Monitoring Initializing the Mdio Module Mdio Module Operational Overview Example of Mdio Register Access Code Writing Data to a PHY RegisterReading Data From a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access Macros Receive Fifo Emac ModuleEmac Module Components Receive DMA Engine Transmit Fifo MAC ReceiverReceive Address Transmit DMA Engine Emac Module Operational Overview Clock and Reset Logic Receive Inter-Frame Interval Media Independent InterfacesData Reception Receive Control Ieee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Interpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APO Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Hardware Receive QOS Support Receive Channel Addressing Host Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive Mode Middle of Frame Overrun Treatment Receive Overrun Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit Latency Transfer Node Priority Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Initialization Enabling the EMAC/MDIO PeripheralEmac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Statistics Interrupt Receive Packet Completion Interrupts Link Change Interrupt Host Error InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and Requests Interrupt Multiplexing Power ManagementEmulation Considerations Proper Interrupt Processing Introduction Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Tcnt Ewint Management Data Input/Output Mdio Registers Modid Mdio Version Register VersionMdio Version Register Version Field Descriptions Modid Revmaj Revmin Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register Link Field Descriptions PHY Link Status Register Link 31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Clear Userintmask Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Phyadrmon Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Maccontrol MacconfigSoftreset RX7FREEBUFFER TX7CP RxcrcerrorsRxaligncodeerrors TX6CP Rxmofoverruns FRAME1024TUPNetoctets Rxsofoverruns Transmit Identification and Version Register Txidver Txident Txmajorver TxminorverTxident Transmit Control Register Txcontrol Transmit Control Register Txcontrol Field DescriptionsTxen Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Rxident Rxmajorver RxminorverRxident Receive Control Register Rxcontrol Receive Control Register Rxcontrol Field DescriptionsRxen Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register Macinvector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Host Stat Pend MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Statmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask Hostmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen Rxcafen Rxbroaden RxbroadchRxmulten RXCH7EN Receive Unicast Enable Set Register RxunicastsetRxmultch RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register Rxbufferoffset RxbufferOffset Rxfilterthresh Thresh Reserved RX nFLOW Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Txpace CmdidleTxptype GIG Txerrch MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions Txerrcode Rgmiifull RxerrcodeRxerrch Rgmiigig Soft Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Soft Free Txcellthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions Rxfifoflowthresh Txcelldepth MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Txcelldepth Rxcelldepth Addresstype Maccfig Soft Reset Register Softreset Field Descriptions Soft Reset Register Softreset MAC Source Address Low Bytes Register Macsrcaddrlo MACSRCADDR0 MACSRCADDR1MACSRCADDR0 MAC Source Address High Bytes Register Macsrcaddrhi MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5MACSRCADDR2 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2 Collcount Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Rndnum Paceval Transmit Pacing Algorithm Test Register Tpacetest Receive Pause Timer Register Rxpause Receive Pause Timer Register Rxpause Field DescriptionsPausetimer Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register Txpause Valid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Match Channel Filt MACADDR0 MACADDR1 MAC Address High Bytes Register Macaddrhi MACADDR2 MACADDR3 MACADDR4 MACADDR5MACADDR2 MAC Index Register Macindex Field Descriptions MAC Index Register Macindex TX nHDP RX nHDP Transmit Channel n Completion Pointer Register TX nCP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel n Completion Pointer Register RX nCP Receive Channel 0-7 Completion Pointer Register RXnCP Broadcast Receive Frames Register Rxbcastframes Network Statistics RegistersStatistics Register Field Descriptions Good Receive Frames Register Rxgoodframes Pause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Multicast Receive Frames Register Rxmcastframes Receive Frame Fragments Register Rxfragments Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register Rxundersized Good Transmit Frames Register Txgoodframes Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register Rxoctets Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register Txpauseframes Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register Txmulticoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Term Definition Table A-1. Physical Layer Definitions Table B-1. Document Revision History Appendix B Revision History Important Notice