Texas Instruments TMS320C645x DSP specification

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EMAC Port Registers

5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

	The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 56 and
	described in Table 56.
	Figure 56. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31	16
	Reserved
	R-0
15	0
	RXnFREEBUF

WI-0

tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; -n= value after reset

Table 56. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15-0	RXnFREEBUF		Receive free buffer count. These bits contain the count of free buffers available. The
			RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
			filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
			control should be issued against incoming packets (if enabled). This is a write-to-increment field.
			This field rolls over to zero on overflow. If hardware flow control or QOS is used, the host must
			initialize this field to the number of available buffers (one register per channel). The EMAC
			decrements (by the number of buffers in the received frame) the associated channel register for
			each received frame. The host must write this field with the number of buffers that have been freed
			due to host processing.

112

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRU975B –August 2006

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Texas Instruments TMS320C645x DSP manual Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix a Appendix B List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Industry Standards Compliance Statement Clock Control MII ClockingRmii Clocking Gmii Clocking Memory Map Rgmii Clocking System Level Connections Interface Selection PinsMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface MtxenMrxdv Control Mtxen Mcrsdv Mrefclk Reduced Media Independent Interface Rmii ConnectionsMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Gigabit Media Independent Interface Gmii Connections Mtclk Gmtclk Emac and Mdio Signals for Gmii Interface Signal Name Description Txctl Refclk RXC TXCRxctl Mdclk Mdio Emac and Mdio Signals for Rgmii Interface TXC Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Multiple Access Protocol Packet Buffer Descriptors Programming InterfaceBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Descriptor in C Structure FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRC Next Descriptor Pointer Buffer PointerBuffer Offset Buffer Length End of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure Format Next Descriptor Pointer Jabber Flag Oversize Flag Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Fragment Flag Emac Control Module Internal MemoryBus Arbiter CPU Interrupt Control Management Data Input/Output Mdio ModuleMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Mdio Module Operational Overview Initializing the Mdio Module Writing Data to a PHY Register Example of Mdio Register Access CodeReading Data From a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadr Emac Module Emac Module ComponentsReceive DMA Engine Receive Fifo MAC Receiver Receive AddressTransmit DMA Engine Transmit Fifo Clock and Reset Logic Emac Module Operational Overview Media Independent Interfaces Data ReceptionReceive Control Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow Control Transmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Packet Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Channel Addressing Hardware Receive QOS Support Receive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment Summary Receive Overrun Middle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel Teardown Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Transfer Node Priority Enabling the EMAC/MDIO Peripheral InitializationEmac Control Module Initialization Mdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Statistics Interrupt Host Error Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change Interrupt Power Management Emulation ConsiderationsProper Interrupt Processing Interrupt Multiplexing Emac Control Module Interrupt Control Register Ewctl IntroductionEmac Control Module Registers Ewint Tcnt Management Data Input/Output Mdio Registers Mdio Version Register Version Mdio Version Register Version Field DescriptionsModid Revmaj Revmin Modid Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link PHY Link Status Register Link Field Descriptions 31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Userintmask Clear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Macconfig SoftresetRX7FREEBUFFER Maccontrol Rxcrcerrors RxaligncodeerrorsTX6CP TX7CP FRAME1024TUP NetoctetsRxsofoverruns Rxmofoverruns Txident Txmajorver Txminorver Transmit Identification and Version Register TxidverTxident Transmit Control Register Txcontrol Field Descriptions Transmit Control Register TxcontrolTxen Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxident Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Receive Control Register Rxcontrol Field Descriptions Receive Control Register RxcontrolRxen Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field Descriptions Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw Host Stat Pend MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Mask Set Register Macintmaskset Host Stat MaskHostmask Statmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen Rxpromch Rxbroadch RxbroadenRxmulten Receive Unicast Enable Set Register Rxunicastset RxmultchRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field Descriptions Rxbuffer Receive Buffer Offset Register RxbufferoffsetOffset Rxfilterthresh Reserved RX nFLOW Thresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Cmdidle TxptypeGIG Txpace MAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsTxerrcode Txerrch Rxerrcode RxerrchRgmiigig Rgmiifull Emulation Control Register Emcontrol Emulation Control Register Emcontrol Field DescriptionsSoft Free Soft Fifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsRxfifoflowthresh Txcellthresh MAC Configuration Register Macconfig MAC Configuration Register Macconfig Field DescriptionsTxcelldepth Rxcelldepth Addresstype Maccfig Txcelldepth Soft Reset Register Softreset Soft Reset Register Softreset Field Descriptions MACSRCADDR0 MACSRCADDR1 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Back Off Test Register Bofftest Field DescriptionsRndnum Collcount Transmit Pacing Algorithm Test Register Tpacetest Paceval Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpausePausetimer Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 Valid MACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMACADDR2 MAC Index Register Macindex MAC Index Register Macindex Field Descriptions TX nHDP RX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TX nCP Receive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RX nCP Network Statistics Registers Statistics Register Field DescriptionsGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Filtered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Table A-1. Physical Layer Definitions Term Definition Appendix B Revision History Table B-1. Document Revision History Important Notice