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Texas Instruments TMS320C645x DSP Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER

Models: TMS320C645x DSP

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EMAC Port Registers

5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

	The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 56 and
	described in Table 56.
	Figure 56. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31	16
	Reserved
	R-0
15	0
	RXnFREEBUF

WI-0

tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; -n= value after reset

Table 56. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15-0	RXnFREEBUF		Receive free buffer count. These bits contain the count of free buffers available. The
			RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
			filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
			control should be issued against incoming packets (if enabled). This is a write-to-increment field.
			This field rolls over to zero on overflow. If hardware flow control or QOS is used, the host must
			initialize this field to the number of available buffers (one register per channel). The EMAC
			decrements (by the number of buffers in the received frame) the associated channel register for
			each received frame. The host must write this field with the number of buffers that have been freed
			due to host processing.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRU975B –August 2006

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Texas Instruments TMS320C645x DSP manual Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramIndustry Standards Compliance Statement Clock Control MII ClockingRmii Clocking Gmii ClockingMemory Map Rgmii ClockingSystem Level Connections Interface Selection PinsMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface MtxenMrxdv ControlMtxen Mcrsdv Mrefclk Reduced Media Independent Interface Rmii ConnectionsMrxer Mdclk Mdio Emac and Mdio Signals for Rmii Interface Gigabit Media Independent Interface Gmii Connections Mtclk GmtclkEmac and Mdio Signals for Gmii Interface Signal Name DescriptionTxctl Refclk RXC TXCRxctl Mdclk Mdio Emac and Mdio Signals for Rgmii Interface TXCEthernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Multiple Access Protocol Packet Buffer Descriptors Programming InterfaceBasic Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Descriptor in C Structure FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRCNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure FormatNext Descriptor Pointer Jabber Flag Oversize FlagCode Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Fragment FlagEmac Control Module Internal MemoryBus Arbiter CPUInterrupt Control Management Data Input/Output Mdio ModuleMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio ModuleWriting Data to a PHY Register Example of Mdio Register Access CodeReading Data From a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadrEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoMAC Receiver Receive AddressTransmit DMA Engine Transmit FifoClock and Reset Logic Emac Module Operational OverviewMedia Independent Interfaces Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Channel Addressing Hardware Receive QOS SupportReceive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Overrun Middle of Frame Overrun TreatmentTransmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsHardware Reset Considerations Transfer Node PriorityEnabling the EMAC/MDIO Peripheral InitializationEmac Control Module Initialization Mdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Statistics InterruptHost Error Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change InterruptPower Management Emulation ConsiderationsProper Interrupt Processing Interrupt MultiplexingEmac Control Module Interrupt Control Register Ewctl IntroductionEmac Control Module Registers Ewint TcntManagement Data Input/Output Mdio Registers Mdio Version Register Version Mdio Version Register Version Field DescriptionsModid Revmaj Revmin ModidMdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field DescriptionsPHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Userintmask ClearMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Macconfig SoftresetRX7FREEBUFFER MaccontrolRxcrcerrors RxaligncodeerrorsTX6CP TX7CPFRAME1024TUP NetoctetsRxsofoverruns RxmofoverrunsTxident Txmajorver Txminorver Transmit Identification and Version Register TxidverTxident Transmit Control Register Txcontrol Field Descriptions Transmit Control Register TxcontrolTxen Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxident Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Receive Control Register Rxcontrol Field Descriptions Receive Control Register RxcontrolRxen Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw Host Stat PendMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedMAC Interrupt Mask Set Register Macintmaskset Host Stat MaskHostmask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchRxbroadch RxbroadenRxmulten Receive Unicast Enable Set Register Rxunicastset RxmultchRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field DescriptionsRxbuffer Receive Buffer Offset Register RxbufferoffsetOffset Rxfilterthresh Reserved RX nFLOW ThreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsCmdidle TxptypeGIG TxpaceMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsTxerrcode TxerrchRxerrcode RxerrchRgmiigig RgmiifullEmulation Control Register Emcontrol Emulation Control Register Emcontrol Field DescriptionsSoft Free SoftFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsRxfifoflowthresh TxcellthreshMAC Configuration Register Macconfig MAC Configuration Register Macconfig Field DescriptionsTxcelldepth Rxcelldepth Addresstype Maccfig TxcelldepthSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMACSRCADDR0 MACSRCADDR1 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field DescriptionsMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Back Off Test Register Bofftest Field DescriptionsRndnum CollcountTransmit Pacing Algorithm Test Register Tpacetest PacevalReceive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpausePausetimer Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 ValidMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMACADDR2 MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTX nHDP RX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TX nCPReceive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RX nCPNetwork Statistics Registers Statistics Register Field DescriptionsGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register RxpauseframesReceive Oversized Frames Register Rxoversized Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsFiltered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesBroadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 144 Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionAppendix B Revision History Table B-1. Document Revision HistoryImportant Notice