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MDIO Registers
4.3MDIO Control Register (CONTROL)
The MDIO control register (CONTROL) is shown in Figure 17 and described in Table 16.
Figure 17. MDIO Control Register (CONTROL)
31 | 30 | 29 | 28 | 24 | 23 | 21 | 20 | 19 | 18 | 17 | 16 |
IDLE | ENABLE | Reserved | HIGHEST_USER_CHANNEL | Reserved |
| PREAMBLE | FAULT | FAULT | Reserved | ||
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| ENB |
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15 |
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| 0 |
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| CLKDIV |
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LEGEND: R/W = Read/Write; R = Read only; |
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Table 16. MDIO Control Register (CONTROL) Field Descriptions
Bit | Field | Value | Description |
31 | IDLE |
| State machine IDLE status bit |
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| 0 | State machine is not in idle state |
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| 1 | State machine is in idle state |
30 | ENABLE |
| State machine enable control bit. . If the MDIO state machine is active at the time it is disabled, it |
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| will complete the current operation before halting and setting the idle bit. |
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| 0 | Disables the MDIO state machine |
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| 1 | Enable the MDIO state machine |
29 | Reserved | 0 | Reserved |
HIGHEST_USER |
| Highest user channel that is available in the module. It is currently set to 1. This implies that | |
| _CHANNEL |
| MDIOUserAccess1 is the highest available user access channel. |
Reserved | 0 | Reserved | |
20 | PREAMBLE |
| Preamble disable |
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| 0 | Standard MDIO preamble is used |
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| 1 | Disables this device from sending MDIO frame preambles |
19 | FAULT |
| Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto |
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| them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it |
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| clears this bit. |
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| 0 | No failure |
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| 1 | Physical layer fault; the MDIO state machine is reset |
18 | FAULTENB |
| Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection. |
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| 0 | Disables the physical layer fault detection |
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| 1 | Enables the physical layer fault detection |
Reserved | 0 | Reserved | |
CLKDIV |
| Clock Divider bits. This field specifies the division ratio between VBUS peripheral clock and the | |
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| frequency of MDCLK. MDCLK is disabled when CLKDIV is set to 0. MDCLK frequency = peripheral |
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| clock frequency/(CLKDIV + 1). |
68 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | SPRU975B |
