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EMAC Functional Architecture
2EMAC Functional Architecture
This chapter discusses the architecture and basic function of the EMAC peripheral.
2.1Clock Control
The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as shown below:
∙2.5 Mhz at 10 Mbps
∙25 Mhz at 100 Mbps
∙125 MHz at 1000 Mbps
The C645x device uses two PLL controllers to generate all of the clocks that the DSP needs. The primary PLL controller generates a peripheral clock (SYSCLK2) that several peripherals use, including the EMAC. SYSCLK2 runs at a rate equal to 1/6th of the CPU clock frequency (CPUclk/6), and is not programmable.
The secondary PLL controller conveniently generates a reference clock (SYSCLK1). The EMAC uses the SYSCLK1 to generate the transmit and receive clocks for the GMII and RGMII interfaces. The frequency of SYSCLK1 is equal to the secondary PLL controller’s input clock (25 MHz) multiplied by 10 and divided by either 5 or 2. You must program SYSCLK1 to the correct frequency based on the interface that you are using (as determined by the configuration pins MACSEL[1:0]). See Section 2.1.1, Section 2.1.3, and Section 2.1.4 for the configuration of SYSCLK1 that is required on each interface.
Note: The RGMII interface does not require an interface clock. However, a reference clock that is derived from SYSCLK1 is provided for your convenience. The reference clock is not a free running clock. The reference clock stops while the DSP is in reset; therefore, you must be careful if you use this clock elsewhere in the system.
The MDIO clock is based on a
2.1.1MII Clocking
When you select the MII clocking interface by setting MACSEL to the default value (00b), the transmit and receive clock sources are provided from an external PHY via the MTCLK and MRCLK pins. These clocks are inputs to the EMAC module and operate at 2.5 MHz in 10 Mbps mode, and at 25 MHz in 100 MHz mode. The MII clocking interface is not used in 1000 Mbps mode. For timing purposes, data is transmitted and received with reference to MTCLK and MRCLK, respectively.
2.1.2RMII Clocking
When you select the RMII interface by setting MACSEL to 01b, you must provide a 50MHz reference clock through the MREFCLK pin. The EMAC clocks the transmit and receive operations from the reference clock. The MTCLK and MRCLK device pins are not used for this interface. The RMII protocol turns one data phase of an MII transfer into two data phases at double the clock frequency. This is the driving factor for the 50 MHz reference clock. Data at the IO pins are running at 5 MHZ in 10 Mbps mode, and at 50 MHz in 100 Mbps mode.
2.1.3GMII Clocking
When you set MACSEL to 02b to select GMII, the transmit and receive clock sources for 10/100 Mbps modes are provided from an external PHY via the MTCLK and MRCLK pins. For 1000 Mbps mode, the receive clock is provided by an external PHY via the MRCLK pin. For transmit in 1000 Mbps mode, the clock is sourced synchronous with the data, and is provided by the EMAC to be output on the GMTCLK pin.
The SYSCLK1 of the secondary PLL controller sources the GMTCLK. The divider generating SYSCLK1 needs to be programmed to /2 (the default value) for this interface to provide a 125 MHz clock to the EMAC.
14 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | SPRU975B |
