MAC Control Register Maccontrol | Texas Instruments TMS320C645x DSP

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EMAC Port Registers

5.29 MAC Control Register (MACCONTROL)

The MAC control register (MACCONTROL) is shown in Figure 57 and described in Table 57.

Figure 57. MAC Control Register (MACCONTROL)

31							24
				Reserved
				R-0
23				19	18	17	16
		Reserved			RGMIIEN	GIGFORCE	RMIIDUPLEX-
							MODE
		R-0			R/W-0	R/W-0	R/W-0
15	14	13	12	11	10	9	8
RMIISPEED	RXOFFLENBLOCK	RXOWNERSHIP	RXFIFO	CMDIDLE	Reserved	TXPTYPE	Reserved
			FLOWEN
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R-0	R/W-0	R-0
7	6	5	4	3	2	1	0
GIG	TXPACE	GMIIEN	TXFLOWEN	RXBUFFERFLOWEN	Reserved	LOOPBACK	FULLDUPLEX
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R-0	R/W-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 57. MAC Control Register (MACCONTROL) Field Descriptions

Bit	Field	Value	Description
31-19	Reserved	0	Reserved
18	RGMIIEN		RGMII enable bit. Enables the fullduplex and gigabit mode to be selected from the
			RGMIIFULLDUPLEX and RGMIIGIG input signals and not from the FULLDUPLEX and GIG bits
			contained in this register. This bit is directly connected to the RXINBAND input on the RGMII
			module.
		0	The RGMII interface is in forced link mode. The duplexity is determined by the FULLDUPLEX
			bit, and the speed is determined by the GIG bit. The speed is either 1 Gbps or 100 Mbps; 10
			Mbps is not supported in forced link mode.
		1	The RGMII interface requires and uses the in-band signals coming in on its receive.
17	GIGFORCE		Gigabit force mode. This bit is used to force the EMAC into gigabit mode if the input MTCLK
			signal has been stopped by the PHY.
16	RMIIDUPLEXMODE		Duplex mode for the RMII interface.
		0	The RMII operates in half duplex mode
		1	The RMII operates in full duplex mode. This mode is not supported in the C645x devices.
15	RMIISPEED		Operating speed for the RMII interface
		0	The RMII operates at 2.5 MHz (10Mbps mode)
		1	The RMII operates at 25 MHz (100 Mbps mode)
14	RXOFFLENBLOCK		Receive offset / length word write block
		0	Do not block the DMA writes to the receive buffer descriptor offset/buffer length word
		1	Block all EMAC DMA controller writes to the receive buffer descriptor offset/buffer length words
			during packet processing. When this bit is set, the EMAC will never write the third word to any
			receive buffer descriptor.
13	RXOWNERSHIP		Receive ownership write bit value
		0	The EMAC writes the Receive ownership bit to zero at the end of packet processing
		1	The EMAC writes the Receive ownership bit to one at the end of packet processing. If you do
			not use the ownership mechanism, you can set this mode to preclude the necessity of software
			having to set this bit each time the buffer descriptor is used.
12	RXFIFOFLOWEN		Receive FIFO flow control enable
		0	Receive flow control disabled. For full-duplex mode, no outgoing pause frames are sent.
SPRU975B –August 2006			Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	113
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Texas Instruments TMS320C645x DSP manual MAC Control Register Maccontrol Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents Receive Unicast Clear Register Rxunicastclear Appendix B Appendix a List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Industry Standards Compliance Statement MII Clocking Clock ControlRmii Clocking Gmii Clocking Rgmii Clocking Memory Map Media Independent Interface MII Connections Interface Selection PinsSystem Level Connections Mtxen Emac and Mdio Signals for MII InterfaceMrxdv Control Mrxer Mdclk Mdio Reduced Media Independent Interface Rmii ConnectionsMtxen Mcrsdv Mrefclk Emac and Mdio Signals for Rmii Interface Mtclk Gmtclk Gigabit Media Independent Interface Gmii Connections Signal Name Description Emac and Mdio Signals for Gmii Interface Rxctl Mdclk Mdio TXCTxctl Refclk RXC TXC Emac and Mdio Signals for Rgmii Interface Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Multiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Descriptor in C Structure Format Transmit Buffer Descriptor FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRC Buffer Pointer Next Descriptor PointerBuffer Offset Buffer Length Ownership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Example 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor Format Next Descriptor Pointer Oversize Flag Jabber Flag Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Fragment Flag Internal Memory Emac Control ModuleBus Arbiter CPU Mdio Module Components Management Data Input/Output Mdio ModuleInterrupt Control Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Initializing the Mdio Module Mdio Module Operational Overview Reading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access Macros Emac Module Components Emac ModuleReceive DMA Engine Receive Fifo Receive Address MAC ReceiverTransmit DMA Engine Transmit Fifo Emac Module Operational Overview Clock and Reset Logic Data Reception Media Independent InterfacesReceive Control Receive Inter-Frame Interval Ieee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control CRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Hardware Receive QOS Support Receive Channel Addressing Receive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Receive Frame Treatment Summary Promiscuous Receive Mode Middle of Frame Overrun Treatment Receive Overrun Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel Teardown Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Transfer Node Priority Emac Control Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Example 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Statistics Interrupt Receive Packet Completion Interrupts User Access Completion Interrupt Host Error InterruptMdio Module Interrupt Events and Requests Link Change Interrupt Emulation Considerations Power ManagementProper Interrupt Processing Interrupt Multiplexing Emac Control Module Registers IntroductionEmac Control Module Interrupt Control Register Ewctl Tcnt Ewint Management Data Input/Output Mdio Registers Mdio Version Register Version Field Descriptions Mdio Version Register VersionModid Revmaj Revmin Modid Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register Link Field Descriptions PHY Link Status Register Link 31-2 Linkint Masked Userintraw Will clear the interrupt and writing 0 has no effect Maskset Clear Userintmask Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Softreset MacconfigRX7FREEBUFFER Maccontrol Rxaligncodeerrors RxcrcerrorsTX6CP TX7CP Netoctets FRAME1024TUPRxsofoverruns Rxmofoverruns Txident Transmit Identification and Version Register TxidverTxident Txmajorver Txminorver Txen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Rxident Receive Identification and Version Register RxidverRxident Rxmajorver Rxminorver Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register Macinvector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Host Stat Pend MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Host Stat Mask MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen Rxpromch Rxmulten RxbroadenRxbroadch Rxmultch Receive Unicast Enable Set Register RxunicastsetRXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register Rxmaxlen Offset Receive Buffer Offset Register RxbufferoffsetRxbuffer Rxfilterthresh Thresh Reserved RX nFLOW Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Txptype CmdidleGIG Txpace MAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusTxerrcode Txerrch Rxerrch RxerrcodeRgmiigig Rgmiifull Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolSoft Free Soft Fifo Control Register Fifocontrol Field Descriptions Fifo Control Register FifocontrolRxfifoflowthresh Txcellthresh MAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigTxcelldepth Rxcelldepth Addresstype Maccfig Txcelldepth Soft Reset Register Softreset Field Descriptions Soft Reset Register Softreset MACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2 Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestRndnum Collcount Paceval Transmit Pacing Algorithm Test Register Tpacetest Pausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register Txpause MAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Match Channel Filt MACADDR0 MACADDR1 Valid MACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex Field Descriptions MAC Index Register Macindex TX nHDP RX nHDP Transmit Channel n Completion Pointer Register TX nCP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel n Completion Pointer Register RX nCP Receive Channel 0-7 Completion Pointer Register RXnCP Statistics Register Field Descriptions Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register Rxpauseframes Receive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive QOS Filtered Frames Register Rxqosfiltered Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 144 Appendix a Glossary Term Definition Table A-1. Physical Layer Definitions Table B-1. Document Revision History Appendix B Revision History Important Notice