Texas Instruments TMS320C645x DSP Power Management, Emulation Considerations, Emulation Control

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EMAC Functional Architecture

2.16.3Proper Interrupt Processing

All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, their level remains constant. However, the CPU core requires edge-triggered interrupts. To properly convert the level-driven interrupt signal to an edge-triggered signal, the application software must use the interrupt control logic of the EMAC control module.

Section 2.6.3 discusses interrupt control in the EMAC control module. For safe interrupt processing, the software application should disable interrupts using the EMAC Control Module Interrupt Control (EWCTL) register upon entry to the ISR, and re-enable them upon leaving the ISR. If any interrupt signals are active at that time, this creates another rising edge on the interrupt signal routed to the CPU interrupt controller, thus triggering another interrupt. The EMAC control module also uses the EMAC Control Module Interrupt Timer Count (EWINTTCNT) register to implement interrupt pacing.

2.16.4Interrupt Multiplexing

The EMAC control module combines different interrupt signals from both the EMAC and MDIO modules and generates a single interrupt signal that is wired to the CPU interrupt controller.

Once this interrupt is generated, the reason for the interrupt can be read from the MACINVECTOR register located in the EMAC memory map. MACINVECTOR combines the status of the following 20 interrupt signals: TXPENDn, RXPENDn, STATPEND, HOSTPEND, LINKINT, and USERINT.

The EMAC and MDIO interrupts are combined within the EMAC control module and mapped to system event 17 through the use of the enhanced interrupt selector within the C64x+ core. For more details, see the Interrupt Controller chapter in the TMS320C64x+ Megamodule Peripherals Reference Guide SPRU871.

2.17 Power Management

The power saver module integrated in this device allows the clock going to different peripherals to be shut down when that peripheral is not being used. For more information on the power conservation modes available for the EMAC/MDIO peripheral, see the device-specific data manual.

2.18 Emulation Considerations

EMAC emulation control is implemented for compatibility with other peripherals. The SOFT and FREE bits from the EMCONTROL register allow EMAC operation to be suspended.

When the emulation suspend state is entered, the EMAC will stop processing receive and transmit frames at the next frame boundary. Any frame currently in reception or transmission will be completed normally without suspension. For transmission, any complete or partial frame in the transmit cell FIFO will be transmitted. For receive, frames that are detected by the EMAC after the suspend state is entered are ignored. No statistics will be kept for ignored frames.

Table 10 shows how the SOFT and FREE bits affect the operation of the emulation suspend.

Table 10. Emulation Control

SOFT	FREE	Description
0	0	Normal operation
1	0	Emulation suspend
X	1	Normal operation

SPRU975B –August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 63

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