Fluke 5720A Watchdog Timer, Address Decoding and DTACK Data Acknowledge, 4. CPU Memory Map

5700A/5720A Series II Calibrator

Service Manual

2-33. Watchdog Timer

The watchdog timer circuitry uses a 74HC4020 binary counter (U11) to divide the 450 Hz from the clock generation circuit to produce interrupt DOGINTH, signifying that the system may be locked up. This interrupt is generated 1.14 seconds after the last DOGCLR2 signal from interrupt controller U10. Therefore, DOGCLR2 must occur more often then every 1.14 seconds to clear U11 and prevent the watchdog interrupt. Generation of DOGCLR2 is under software control. The watchdog timer can be disabled by cutting jumper E1.

2-34. Address Decoding and DTACK (Data Acknowledge)

Two Programmable Logic Devices (PLDs) accomplish address decoding and DTACK (data acknowledge) generation. ICs U5 and U6 provide chip selects and generate acknowledgment signals for those devices without DTACK lines. IC U5 receives DTACK signals from the asynchronous devices and ORs these signals together to form DTACK*. Table 2-4 is the memory map for the system. It shows the chip select, address range, and notes whether AS* (address strobe) or LDS* (lower data strobe) is required.

Table 2-4. CPU Memory Map

Chip Select

PROM0CS*

PROM1CS*

PROM2CS*

RAM0CS*

RAM1CS*

RAM2CS*

NVMCS*

MISCCS*

RPSEL*

RPDUARTCS*

RPIEEECS*

Y52XXRD*

Y5205WR*

Y5220WR*

FRNTPNLCS*

OTDCS*

DMDCS* ENCODERCSR ENCODERRESETW LED_OUTPUT_ R LED_LATCH_EN KEYBOARDCS GCDRTCS* XDUARTCS* RDINT* DOGCLR ADCLKCS*

Read/Write

R

R

R

R/W

R/W

R/W

R/W

R/W

R

W

W

R/W

R/W

R/W

R

W

R

R/W

R/W

R/W

W

Address Range

0 to 3FFFF

40000 to 7FFFF

80000 to BFFFF

600000 to 60FFFF

610000 to 61FFFF

620000 to 623FFF

C00000 to CFFFFF

D00000 to DFFFFF

D00000 to D01FFF

D00000 to D0001F

D00020 to D0002F

D00030 to D00031

D00032 to D00033

D00034 to D00035

D02000 to D03FFF

D02000 to D027FF

D02800 to D02FFF

D03000 to D033FF

D03000 to D033FF

D03400 to D037FF

D03400 to D037FF

D03800 to D038FF

D04000 to D05FFF

D06000 to D07FFF

D08000 to D09FFF

D08000 to D09FFF

E00000 to EFFFFF

AS* or LDS* Required?

no no no no no no no no LDS* LDS* LDS* LDS* LDS* LDS* AS* AS* AS* AS* AS*

AS

AS*

AS*

LDS*

LDS*

AS*

even only, AS* AS*

2-24