2-205. Rear Panel Power Supplies

Theory of Operation 2

Analog Section Detailed Circuit Description

2-205. Rear Panel Power Supplies

Power supplies are divided into guarded and unguarded. Unguarded supplies +5V LOGIC, +12V, and -12V are referenced to +5V LOGIC COMMON and are generated on the Digital Power Supply assembly (A19). Guarded supplies +5LH and -5LH are referenced to LH COM, and the supply +5RLH is referenced to RLH COM. These supplies are generated on the Regulator/Guard Crossing assembly (A17). Some ICs on the A17 assembly do not have power and ground pins shown on the schematic. This information is included in the table on sheet 1 of the Rear Panel schematic.

Table 2-16. Divider Settings and VCO Frequencies

Calibrator Output

Frequency at

TP16

10 Hz to 12 Hz

13 Hz to 15 Hz

16 Hz to 30 Hz

31 Hz to 60 Hz

61 Hz to 120 Hz

130 Hz to 150 Hz

160 Hz to 300 Hz

310 Hz to 600 Hz

610 Hz to 1.2 kHz

1.3kHz to 1.5 kHz

1.6kHz to 3.0 kHz

3.1kHz to 6.0 kHz

6.1kHz to 12 kHz 13 kHz to 15 kHz 16 kHz to 30 kHz 31 kHz to 60 kHz 61 kHz to 120 kHz

130 kHz to 150 kHz

U17 R Divider

Setting

500

400

200

100

50

400

200

100

50

400

200

100

50

400

200

100

50

40

U17 N Divider

Setting

1000

1000

1000

1000

1000

100

100

100

100

10

10

10

10

0

0

0

0

0

Total Division

of VCO at

TP13

1M

800k

400k

200k

100k

80k

40k

20k

10k

8k

4k

2k

1k

800

400

200

100

80

VCO Frequency

at TP13

10 MHz to 12 MHz

10.4 MHz to 12 MHz

6.4 MHz to 12 MHz

6.2 MHz to 12 MHz

6.1 MHz to 12 MHz

10.4 MHz to 12 MHz

6.4 MHz to 12 MHz

6.2 MHz to 12 MHz

6.1 MHz to 12 MHz

10.4 MHz to 12 MHz

6.4 MHz to 12 MHz

6.2 MHz to 12 MHz

6.1 MHz to 12 MHz

10.4 MHz to 12 MHz

6.4 MHz to 12 MHz

6.2 MHz to 12 MHz

6.1 MHz to 12 MHz

10.4 MHz to 12 MHz

160 kHz to 300 kHz

310 kHz to 600 kHz

610 kHz to 1.2 MHz

20

0

40

10

 

 

0

20

5

 

 

0

10

 

 

 

6.4 MHz to 12 MHz

6.2 MHz to 12 MHz

6.1 MHz to 12 MHz

2-206. Rear Panel Address Mapping

The rear panel decodes address lines from the bus connected to the main CPU through connector P91. Decoding is accomplished with a C22V10 PLD (U8) with the following chip selects:

RPDUARTCS*, D00000-D0001F

RPIEEECS*, D00020-D0002F

Y52XXRD*, D00030-D00031

Y5205WR*, D00032-D00033

Y5220WR*, D00034-D00035

2-131

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Image 193
Fluke 5720A Rear Panel Power Supplies, Rear Panel Address Mapping, ∙ RPDUARTCS*, D00000-D0001F ∙ RPIEEECS*, D00020-D0002F