MPC5200B Users Guide, Rev. 1
3-4 Freescale Semiconductor
MPC5200B Memory Map
3.3.2.2 LocalPlus Bus
The LocalPlus Bus is designed to connect to ROM, FLASH, static RAM and other peripheral devices. It is not designed to accommodate
DRAM’s. Program execution begins from the LocalPlus Bus memory device connected to LP_CS0. In actual practice, the only programs that
are usually executed from LocalPlus Bus memory are those used to initialize the MPC5200B and to transfer data from LocalPlus Bus memory
to SDRAM bus memory. In general, programs are stored as data in non-volatile memory on the LocalPlus Bus and then transferred to the
SDRAM Bus. Once the transfer occurs, program execution is transferred to a program residing in memory on the SDRAM Bus.
The LocalPlus Bus can be accessed by the CPU to perform direct reads and writes of external memory or the LocalPlus Bus can be a
BestComm Peripheral. In this case, the CPU programs the BestComm Controller to automatically transfer data from a particular source
address to the LocalPlus memory or from the LocalPlus memory to a particular destination address. Almost all peripheral modules, such as
the PSC modules, and both the SDRAM Bus and LocalPlus Bus can be BestComm data sources or destinations.
There are 8 chip select lines, CS0 - CS7, associated with the LocalPlus Bus. Also, there are three basic memory access types that can be run
on the LocalPlus bus. These are normal memory accesses, PCI cycles and ATA cycles.
The LocalPlus LP_CS0 pin can have two configurations. It can be the BOOT Chip Select line, which is its default condition from the release
of RESET, and it can be configured after RESET to be LP_CS0. When configured as the BOOT Chip Select, this chip select line can select
Program Space. Thus, program execution can occur from the memory device selected by LP_CS0. If the LP_CS0 pin is configured for data
space by user software, then only Data Space Memory can be read or written.
Associated with each Chip Select line is a Start Address Register and a Stop Address Register. There are two Chip Select Start/Stop Address
Register pairs associated with the LP_CS0 pin. One Chip Select Start/Stop Register pair is used to configure the LP_CS0 pin as the BOOT
Chip Select and the other register pair configures the LP_CS0 pin to run normal memory access cycles in data space, only. Only one of the
LP_CS0 Chip Select Start/Stop Address Register pairs should be active at any given time.
When enabled as the Boot Chip Select, only reads are possible. Reads of 64-bits are supported for instruction fetches. Burst reads are also
supported. When enabled as a data space memory chip select, only Data Space reads and writes are supported. Code cannot be executed from
a memory device connected to LP_CS0 when it is configured as a data space chip select. Bursting is not supported and reads are limited to
32-bits.
There are two additional Start/Stop Address Register pairs used for PCI cycles. These registers are not associated with any chip select line.
Chip Select 4 and Chip Select 5 can be configured to run normal memory cycles or ATA cycles. Chip Select 1 - 3 and Chip Select 6 - 7 can
only run normal memory cycles.
All the address related registers in this module are in the form of Start/Stop pairs. An address appearing on XL Bus is compared as
equal-to-or-greater than the Start value and less-than-or-equal-to the Stop value. If both tests pass then a valid address “hit” occurs for the
associated space. For Start values the unused bits are assumed to be zero, for Stop values the unused bits are assumed to be high.
Address registers (and the MBAR itself) have only 16 significant bits. Although these bits are right-justified in the registers they are actually
interpreted as the most significant 16 bits of the address for comparison tests. For this reason, software must right shift an absolute address by
16 before writing it as a value into the desired START or STOP Address register. The same is true when reading values from these registers.
Start/Stop comparisons are enabled only if the corresponding enable bit in the MM Address Space Enable Register is high. The proper method
for updating Start/Stop registers is to first write the enable bit to zero, update both the Start and Stop registers, and then re-enable the
corresponding enable bit by writing it high.
NOTE
Failure to follow the above procedure could result in bus hanging and machine check errors.