Freescale Semiconductor MPC5200B 1.2.2 BestComm I/ O Subsystem, 1.2.3 Controller Area Network (CAN)

MPC5200B Users Guide, Rev. 1

1-6 Freescale Semiconductor

Architecture

Up to 3 instructions can be issued and retired per clock. Most instructions execute in a single cycle. The core contains an integrated Floating

Point Unit (FPU), a Data Cache Memory Management Unit and an Instruction Cache Memory Management Unit.. The core implements the

32-bit portion of the PowerPC architecture, which provides 32-bit effective addressing and integer data types of 8-, 16-, and 32-bits.

Enhancements in this core version, specific to embedded automotive/telematics include:

• Improved interrupt latency (critical interrupt)

• New MMU with additional 8 BAT (16 total) registers and 1KByte page management

The e300 core performance for SPEC95 benchmark integer operations, ranges between 4.4 and 5.1 at 200MHz. In Drystone 2.1 MIPS, the

e300 core is 280MIPS at 200MHz.

1.2.2 BestComm I/ O Subsystem

BestComm contains an intelligent DMA unit. This unit provides a front-line interrupt control and data movement interface via a separate

peripheral bus to the on-chip peripheral functions. This leaves the e300 core free for higher level activities. The concurrent operation enables

a significant boost in overall systems performance.

BestComm supports up to 16 simultaneously enabled DMA tasks from up to 32 DMA requestors. Also included is:

• a hardware logic unit

• a hardware CRC unit

BestComm uses internal buffers for prefetched reads and post writes. Bursting is used whenever possible. This optimizes both internal and

external bus activity.

The MPC5200B supports six PSCs. Each can be configured to operate in different modes. PSCs support both synchronous and asynchronous

protocols. They are used to interface to external full-function modems or external CODECs for soft modem support. 8, 16, 24 and 32-bit data

widths are supported. PSCs can be configured to support 1200 baud POTS modem, SPI, I2S, V.34 or V.90 protocols. The standard UART

interface supports connection to an external terminal/computer for debug support.

The Ethernet Controller supports the following standard MAC-PHY interfaces:

• 100Mbps IEEE 802.3 MII

• 10Mbps IEEE 802.3 MII

• 10Mbps 7-wire interface

The controller is full duplex, supports a programmable maximum frame length and retransmission from the Tx FIFO following a collision.

The MPC5200B supports two USB channels. The USB Controller implements the USB Host Controller/Root Hub in compliance with the

USB1.1 specification. The user may choose to have either one or two USB ports on the root hub, each of which can interface to an off-chip

USB transceiver. The Host Controller supports the Open Host Controller Interface (OHCI) standard.

The MPC5200B supports the IrDA format. All three IrDA modes are supported (SIR, MIR, FIR) to 4.0Mbps. The required 48MHz clock can

be generated internally or supplied externally on an input pin.

The MPC5200B supports two I2C channels. Both master and slave interfaces can be controlled directly by the processor or can use the

BestComm Controller to buffer Tx/Rx data when the I2C data rate is high.

The SPI module allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices. It supports master

and slave mode, double-buffered operation and can operate in a polling or interrupt driven environment.

1.2.3 Controller Area Network (CAN)

The MPC5200B supports two CAN channels. The CAN is an asynchronous communications protocol used in automotive and industrial

control systems. It is a high speed, short distance, priority based protocol that runs on a variety of mediums. For example, transmission media

of fiber optic cable or unshielded twisted wire pairs can be used.