MPC5200B Users Guide, Rev. 1
15-52 Freescale Semiconductor
PSC Operation Modes
The source for the internal clock generation is the MclkDiv clock divider in CDM module. The CDM provides for each Codec PSC (1, 2, 3
and 6) a separate Mclk and MclkDiv clock divider. For more information about the fsystem clock see also Section 5.5.11, PSC1 Mclock Config
Register—MBAR + 0x0228. The PSC provides the clock to the external Codec divided independently whether the PSC configured as a master
(provide BitClk and FrameSync) or as a slave (receive the clock signals). These dividers generate the Mclks by dividing the fsystem clock as
follows:
Each PSC consists of an CCR register to generate a BitClk and a FrameSync signal. If the PSC is configured as a master and all necessary
register (cdm_pscX_bitclk_config and CCR) are set to the right value the PSC generate both clock signals independent if the transmitter or
receiver is enabled or not. As opposed to the SPI behavior. The equations below shows the calculation:
When the FrameSync is an output the pulse width can programmed by the register CTUR. This register defines the number of BitClk cycle
during the FrameSync signal is active. The default reset value for this register is 0x00 therefore the default FrameSync width is one BitClk.
See the calculation below:

15.3.2.3 Transmitting and Receiving in “Soft Modem” Codec Mode

The PSC supports the full duplex “soft modem“ mode, data will be received and transmitted at the same time. To start the full duplex
transmission, the Tx and the Rx must be enable by writing the according value to the CR register. Also it’s possible to use only the receiver.
For this case only the Rx enable bit in the CR register must be set to one. But it’s not possible to use the transmitter without the receiver. To
transmit data only, also the receiver must be enabled. The received data and the according status and interrupt bits can be ignored.
If the receiver is enabled, the PSC samples data from the receive line after detecting the start of frame condition. The receiver converts the
serial data from the RX line to parallel data words and write the data to the RxFIFO. The data word length is depend on the programmed word
length. If are no data on the Rx line the receiver writes zeros to the RxFIFO until the data word width was reached. The receiver waits until
the next start of frame condition was detected. The transmitter converts the parallel data from the TxFIFO to a serial data stream on the TX
line. If the TxFIFO is empty during the transmit state, the Tx line will be zero. If the last bit of the data word was send then the transmitter
waits until the next start of frame condition was detected.
When SICR[GenClk] = 1 then the PSC is in master mode and generate the BitClk and the FrameSync signal from the internal clock system,
like described in Section 15.3.2.2, Codec Clock and FrameSync Generation.
Figure 15-9 shows a Codec interface diagram example for “Soft Modem” master mode. The different parameter to define the interface are
follows:
• Frame Sync Polarity SICR[SyncPol], the leading edge is defined as a rising edge if bit SICR[SyncPol] = 1, or a falling edge if
SICR[SyncPol] = 0
• BitClk Polarity SICR[ClkcPol], when bit SICR[ClkPol] = 0 data is shifted out on the rising edge of bit clock and sampled on the
falling edge of BitClk otherwise data is shifted out on the falling edge and sampled on rising edge of bit clock
• FrameSync width CTUR, define the number of BitClk during the FrameSync is active
• FrameSync length CCR[FrameSyncDiv], define the number of BitClk until the next frame starts
• Data length SICR[SIM], define the data with of the receive and transmit data, 8, 16,24 or 32 bit per word are possible, in Codec 24
mode each 24-bit data sample uses an entire 32-bit longword in the Tx FIFO. The least significant (right-hand) byte is not used, data
should be written to the Tx FIFO four bytes at a time.
• Delay of time slot 1 SICR[DTS1], the PSC starts to send a sample at either the leading edge of FrameSync SICR[DTS1] = 0, or 1
bit-clock cycle after the leading edge of FrameSync SICR[DTS1] = 1
Mclk = MclkDiv [8:0] +1
fsystem
BitClk = CCR[8:15] +1
Mclk
Frame = CCR[0:7] +1
BitClk
Frame sync width = CTUR[0:7] + 1