Freescale Semiconductor MPC5200B 18.4 Initialization Sequence, 18.5 Transfer Initiation and Interrupt

Initialization Sequence
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 18-19
An I2C glitch filter has been added outside the I2C legacy modules (but within the I2C package). This filter can absorb (or “eat”) glitches on
both the I2C clock and data lines for each I2C module. The width of glitch to absorb can be specified in terms on number of IPBUS clock
cycles. A single glitch filter control register is provided for both I2C modules.
The programming of the glitch filter is simple - the programmer only needs to specify the size of glitch (in terms of IPBUS clock cycles) for
the filter to absorb and not pass.
18.4 Initialization Sequence
Reset puts the I2C Control register to its default status. Before the interface can be used to transfer serial data, the following initialization
procedure must be done:
Step 1. Update the Frequency Divider register and select the required division ratio to obtain the SCL frequency from the system clock.
Step 2. Update the I2C Address register to define a slave address.
Step 3. Set the Control register EN bit to enable the I2C interface system.
Step 4. Modify the Control register bits to select master /slave mode, transmit/receive mode and interrupt enable or not.
18.5 Transfer Initiation and Interrupt
In master transmit mode, a data transfer is initiated when data is written to the DATA register. The most significant bit is sent first.
In master receive mode, reading this register initiates next byte data receiving.
In slave mode, the same functions as are available after an address match occurs. Data transfer is initiated by:
• writing to the DATA register for slave transmits, or
• a dummy reading from the DATA register in slave receive mode occurs.
The I2C interrupt STATUS register bit is set when an interrupt is pending. If the CONTROL register interrupt enable bit is set, setting the I2C
interrupt STATUS register bit causes a processor interrupt request. The interrupt bit sets when one of the following events occurs:
• A complete 1Byte transfer (set at falling edge of 9th clock) occurs.
• A receive calling address matches its own specific address in slave receive mode.
• Arbitration is lost.
18.5.1 Post-Transfer Software Response
In the interrupt service routine, software must clear the IF status bit first. The CF status bit will be cleared automatically by reading from the
Data I/O Register (MBDR) in receive mode or writing to MBDR in transmit mode.
Software may service the bus I/O in the main program by monitoring the IF status bit if the interrupt function is disabled. Polling should
monitor the IF status bit rather than the CF bit since their operation is different when arbitration is lost.
When an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master
receive mode is required, indicated by R/W bit in the DATA register, then the TX control bit should be toggled at this stage.
During slave mode address cycles (AAS = 1) the SRW bit in the STATUS register is read to determine the direction of the subsequent transfer
and the TX control bit is programmed accordingly. For slave mode, data cycles (AAS = 0) the SRW bit is not valid, therefore the TX bit in
the control register should be read to determine the direction of the current transfer.
18.5.2 Slave Mode
In the slave interrupt service routine, the AAS bit should be tested to determine if a calling of its own address was received. If AAS is set,
software should set the Tx/Rx mode select bit (Control register Tx bit ) according to the R/W command bit (SRW). Writing to the
CONTROL register automatically clears AAS. The slave interrupt service routine should also “move” the data, depending on whether its
acting as a transmitter or a receiver, as follows: For a slave transmitter, the slave interrupt service routine must initiate a data transfer by writing
information to the DATA register. For a slave receiver, the slave interrupt service routine must initiate a transfer by performing a dummy read
from the DATA register. The slave drives SCL low between byte transfers. SCL is released when the DATA register is accessed in the required
mode.
In slave transmitter routine, RXAK must be tested before transmitting the next data byte. Setting RXAK means an end of data signal from the
master receiver. After which, software causes a switch from transmitter mode to receiver mode. A dummy read then releases the SCL line
letting the master generate a STOP signal.