MPC5200B Users Guide, Rev. 1
9-10 Freescale Semiconductor
Configuration
• The boot address/exception table can be located at 0x0000 0100 or 0xfff0 0100.
The PowerPC architecture compatible processor core requires 64-bit instruction fetches. During boot code accesses from CS Boot space
on-chip logic is provided to perform enough LocalPlus accesses to accumulate 64-bit instructions to be given to the e300 processor. For
example, before passing the resulting 64-bit instruction to the e300 processor, LocalPlus logic does either:
• 8 accesses to an 8-bit device
• 4 accesses to a 16-bit device
• 2 accesses to a 32-bit device
NOTE
The Boot space supports cached instruction reads and "critical doubleword word first" transactions.
The Boot space does NOT support:
• an 8-bit wide MUXed mode configuration during boot.
After boot, CS Boot space can be programmed to act as other MPC5200B Chip Select spaces (CS0-7). This capability is described in the
sections below.
9.5.2 Chip Selects Configuration
All Chip Selects CS0-7 have the same functionality. Only one CS can be active at any given time. Multiple CS windows should not overlap.
In the case that an address "hit" is located in multiple CS windows, only one CS, the one with the highest priority, becomes active. The CS
with the lowest number has the highest priority (CS0 highest priority, CS7 lowest priority).
CS Boot and CS0 are identical with the exception of their control registers contained in the MPC5200B MMAP register group, see Section
3.3.3.2, Boot and Chip Select Addresses. CS Boot and CS0 are physically the same pins. The difference is that CS Boot is impacted by the
reset configuration and is enabled after reset, so boot is always performed only at CS Boot.
To change from CS Boot to CS0 the CS0 start and stop addresses must be configured and the disable of CS Boot must occur together with the
Enable of CS0 (see example).
ipbi->control_reg = (ipbi->control_reg & ~CSCTRL_BOOT_EN) | CSCTRL_CS0_EN;
Deadcycles from 0 to 3 can be added to any CS read access and will occur in addition to any cycles which already exist. The configuration of
Dead cycles are done by the Chip Select Deadcycle Control Register.
Burst Mode operations are supported on all CS and can be configured by the Chip Select Burst Control Register.
The e300 processor can execute code from all CSs of the LP bus.
CS0-CS7 in MUXed mode:
• Supports 8-, 16- and 32-bit data reads and writes.
• Support of Dynamic bus sizing. This means read and write transactions greater than the defined port size are possible (up to a
maximum of 32 bits).
• The LPC Controller creates multiple transactions at the defined port size to satisfy the transaction size requested up to a maximum
of 32 bits. Transactions less than the defined port size are supported only if the peripheral can decode the TSIZE[0:2] bits, which
indicate the current transaction size.
• 64-bit access is not supported. Internal logic is limited to 32-bits accesses.
• Support of Code execution
CS0-CS7 non-MUXed mode:
• In non-MUXed mode the data port size can be 8, 16 or 32bits.
• Dynamic Bus Sizing for read and write transactions are supported at the defined port sizes. However, transactions that are less than
the port size fail because no control signals exist to alert the peripheral to the current transaction size. TSIZE[1:2] bits are available
in all non-muxed modes on separate pins, if the LPTZ bit is set in the GPS Port Configuration Register—MBAR + 0x0B00.
• Support of Burst access
9.5.3 Reset Configuration
The mode of the LocalPlus interface at boot is controlled by bits in the RST_CONFIG word described in Chapter 4, Resets and Reset
Configuration. The following 6 RST_CONFIG bits control boot device operation from reset:
• BootType
• BootSize
• BootMostGraphics
• BootLargeFlash
• BootWait