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MPC5200B Users Guide, Rev. 1
Freescale Semiconductor A-11
stp . . . . . . . . . . . . . . . . . . . . . stop
str . . . . . . . . . . . . . . . . . . . . . start
STS . . . . . . . . . . . . . . . . . . . . Special Transfer Start
Superscalar machine. . . . . . . A machine that can issue multiple instructions concurrently from a conventional linear instruction stream.
Supervisor mode. . . . . . . . . . The privileged operation state of a processor. In supervisor mode, software (typically the operating system) can
access all control registers and th e supervisor memory space, among other privileged operations.
SWT . . . . . . . . . . . . . . . . . . . Software Watchdog Timer
Synchronization . . . . . . . . . . A process to ensure operations occur in order. See also Context synchronization and Execution synchronization.
Synchronous exception. . . . . An exception generated by the execution of a particular instruction or instruction sequence. There are two types
of synchronous exceptions, precise and imprecise.
System memory . . . . . . . . . . The physical memory available to a processor.
T
TA. . . . . . . . . . . . . . . . . . . . . Transfer Acknowledge
TAP. . . . . . . . . . . . . . . . . . . . Test Access Port
TB. . . . . . . . . . . . . . . . . . . . . Time Base (register )
TC. . . . . . . . . . . . . . . . . . . . . Transmission Convergence
TCT. . . . . . . . . . . . . . . . . . . . Transmit Connection Table
TDM . . . . . . . . . . . . . . . . . . . Time-Division Multiplex—a single serial channel used by several channels taking turns.
TE . . . . . . . . . . . . . . . . . . . . . Terminal Endpoint
TEA. . . . . . . . . . . . . . . . . . . . Transfer Error Acknowledge
Throughput . . . . . . . . . . . . . . A measure of the number of instructions processed per clock cycle.
TLB. . . . . . . . . . . . . . . . . . . . Translation Lookaside Buffer—A cache that holds recently-used page table entries.
TLE. . . . . . . . . . . . . . . . . . . . True Little-Endian
TMR, tmr . . . . . . . . . . . . . . . Timer
TO, to . . . . . . . . . . . . . . . . . . Timeout
TS . . . . . . . . . . . . . . . . . . . . . Transfer Start
TSA. . . . . . . . . . . . . . . . . . . . Time-Slot Assigner
tst. . . . . . . . . . . . . . . . . . . . . . test
TSIZ . . . . . . . . . . . . . . . . . . . Transfer Size
Tx, TX. . . . . . . . . . . . . . . . . . Transmit
U
UART . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver-Transmitter—a component that handles asynchronous serial
communication.
UARTe . . . . . . . . . . . . . . . . . UART enhanced (simple UART with carrier detect input)
UBR . . . . . . . . . . . . . . . . . . . Unspecified Bit-Rate. See also CBR and ABR.
UBR+ . . . . . . . . . . . . . . . . . . Unspecified Bit-Rate with minimum cell rate guarantee
UIMM. . . . . . . . . . . . . . . . . . Unsigned IMMediate value
UISA. . . . . . . . . . . . . . . . . . . User Instruction Set Architecture—the level of the architecture to which user-level software should conform.
The UISA defines the base user-level instruction set, user-level registers, data types, floating-point memory
conventions and exception model as seen by user programs, and the memory and programming models.
UPM . . . . . . . . . . . . . . . . . . . Use r-Programmable Machine
USART . . . . . . . . . . . . . . . . . Universal Synchronous/Asynchronous Rx /Tx
USB. . . . . . . . . . . . . . . . . . . . Universal Serial Bus—a new external bus standard that supports data transfer rates of 12Mbps.
User mode. . . . . . . . . . . . . . . The unprivileged operating state of a processor used typically by application software. In user mode, software
can only access certain control registers and can access only user memory space. No privileged operations can
be performed. Also referred to as problem state.
UTOPIA . . . . . . . . . . . . . . . . Universal Test and Operations Physical Interface for ATM
V
VA. . . . . . . . . . . . . . . . . . . . . Virtual Address—an intermediate address used in tr anslation of an effective address to a physical address.