List of Tables
Tabl e Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor LOT-5
12-8 USB HC Period Current Endpoint Descriptor Register ........................................................................................12-13
12-9 USB HC Control Head Endpoint Descriptor Register ..........................................................................................12-14
12-10 USB HC Control Current Endpoint Descriptor Register ..................................................................................... .12-14
12-11 USB HC Bulk Head Endpoint Descriptor Register ...............................................................................................12-15
12-12 USB HC Bulk Current Endpint Descriptor Register .................................................................... .........................12-15
12-13 USB HC Done Head Register ............................ ....................................................................................... ............12-16
12-14 USB HC Frame Interval Register ............................................................................... ...........................................12-16
12-15 USB HC Frame Remaining Register ..................................................................................... ................................12-17
12-16 USB HC Frame Number Register ............................................... ..........................................................................12-17
12-17 USB HC Periodic Start Register ............... ......................................................................................... ...................12-18
12-18 USB HC LS Threshold Register ...... ....................................................................................... ..............................12-18
12-19 USB HC Rh Descriptor A Register .......................................................... .............................................................12-19
12-20 USB HC Rh Descriptor B Register .................................. .................................................................................... .12-21
12-21 USB HC Rh Status Register ................................................... ...............................................................................12-21
12-22 USB HC Rh Port1 Status Register ..................... ..................................................................................... ..............12-23
12-23 USB HC Rh Port2 Status Register ..................... ..................................................................................... ..............12-26
13-1 SDMA Task Bar Register .................................................................................... ....................................................13-4
13-2 SDMA Current Pointer Register .................. .................................................................................... .......................13-4
13-3 SDMA End Pointer Register ..................................... .................................................................................... ..........13-5
13-4 SDMA Variable Pointer Register ......................................................... ...................................................................13-5
13-5 SDMA Interrupt Vector, PTD Control Register .............. ...................................................................................... .13-6
13-6 SDMA Interrupt Pending Register .............................................. ............................................................................13-6
13-7 SDMA Interrupt Mask Register .................................... ..................................................................................... .....13-7
13-8 SDMA Tas k Control 0 Register ................................... ....................................................................................... ...13-8
13-9 SDMA Task Control 2 Register ............................................. .................................................................................13-9
13-10 SDMA Task Control 4 Register ............................................. ...............................................................................13-10
13-11 SDMA Task Control 6 Register ............................................. ...............................................................................13-10
13-12 SDMA Task Control 8 Register ............................................. ...............................................................................13-11
13-13 SDMA Task Control A Register ................................. ..................................................................................... .....13-11
13-14 SDMA Task Control C Register ............... ....................................................................................... .....................13-12
13-15 SDMA Task Control E Register ..................................................................................... .......................................13-12
13-16 SDMA Initiator Priority 0 Register .......................................... .............................................................................13-13
13-17 SDMA Initiator Priority 4 Register .......................................... .............................................................................13-14
13-18 SDMA Initiator Priority 8 Register .......................................... .............................................................................13-14
13-19 SDMA Initiator Priority 12 Register ........................................... ..........................................................................13-15
13-20 SDMA Initiator Priority 16 Register ........................................... ..........................................................................13-16
13-21 SDMA Initiator Priority 20 Register ........................................... ..........................................................................13-17
13-22 SDMA Initiator Priority 24 Register ........................................... ..........................................................................13-17
13-23 SDMA Initiator Priority 28 Register ........................................... ..........................................................................13-18
13-24 SDMA Request MuxControl ........................................................................... ......................................................13-19
13-25 FIxed REquestors Table ................................................ ........................................................................................ 13-20
13-26 SDMA task Size 0/1 .................................................. ....................................................................................... .....13-21
13-27 SDMA task Size Map .................................................................... ........................................................................13-21
13-28 SDMA Reserved Register 4 ...................................... ......................................................................................... ...13-22
13-29 SDMA Reserved Register 2 ...................................... ......................................................................................... ...13-22
13-30 SDMA Debug Module Comparator 1, Value1 Register .......................................................................................13-22
13-31 SDMA Debug Module Comparator 2, Value2 Register .......................................................................................13-23
13-32 SDMA Debug Module Control Register ...............................................................................................................13-23
13-33 Comparator 1 Type Bit Encoding ............. ....................................................................................... .....................13-24
13-34 Comparator 2 Type Bit Encoding ............. ....................................................................................... .....................13-25
13-35 EU Breakpoint encoding ......................... ....................................................................................... .......................13-25
13-36 SDMA Debug Module Status Register .................................................................................................................13-25
13-37 Behavior of Task Table Control Bits .... ....................................................................................... .........................13-28
13-38 Variable Table per Task ................. ......................................................................................... ..............................13-29