Table of Contents
Paragraph Pa ge
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-9
11.3.3.5 ATA Drive Error Register—MBAR + 0x3A64 ...... .................................................................................11-14
11.3.3.6 ATA Drive Sector Count Register—MBAR + 0x3A68 ...........................................................................11-15
11.3.3.7 ATA Drive Sector Number Register—MBAR + 0x3A6C .................................................. .....................11-15
11.3.3.8 ATA Drive Cylinder Low Register—MBAR + 0x3A70 ................................................ .........................11-16
11.3.3.9 ATA Drive Cylinder High Register—MBAR + 0x3A74 .........................................................................11-16
11.3.3.10 ATA Drive Device/ Head Register—MBAR + 0x3A78 ........... ...............................................................11-17
11.3.3.11 ATA Drive Device Command Register—MBAR + 0x3A7C ..................................................................11-1 7
11.3.3.12 ATA Drive Device Status Register—MBAR + 0x3A7C .........................................................................11-19
11.4 ATA Host Controller Operation ............................................... .............................................................................11-20
11.4.1 PIO State Machine ............ ....................................................................................... .......................................11-21
11.4.2 DMA State Machine . ...................................................................................... ................................................11-22
11.4.2.1 Software Requirements ......................................................... ....................................................................11-22
11.5 Signals and Connections .......................................................................................................................................11-23
11.6 ATA Interface Description ............................. ....................................................................................... ................11-24
11.7 ATA Bus Background .................................................................................................................... .......................11-26
11.7.1 Terminology ....................................................................................................................................................11-26
11.7.2 ATA Modes ....................................................................... .............................................................................11-27
11.7.3 ATA Addressing ........... ....................................................................................... ...........................................11-27
11.7.31 ATA Register Addressing ........................................................................ ................................................11-28
11.7.3.2 Drive Interrupt ................. ...................................................................................... ...................................11-28
11.7.3.3 Sector Addressing ........................................... ..................................................................................... .....11-28
11.7.3.4 Physical/Logical Addressing Modes ........................................................................................ ................11-29
11.7.4 ATA Transactions ........................... .................................................................................... ............................11-30
11.7.4.1 PIO Mode Transactions .............................. ...................................................................................... ........11-30
11.7.4.1.1 Class 1—PIO Read ............................................................................... .............................................11-30
11.7.4.1.2 Class 2—PIO Write ............................................................... .............................................................11-31
11.7.4.1.3 Class 3—Non-Data Command ....................................................... ....................................................11-32
11.7.4.2 DMA Protocol . ....................................................................................... ..................................................11-32
11.7.4.3 Multiword DMA Transactions ............................................................................. ....................................11-35
11.7.4.3.1 Class 4—DMA Command ................ ....................................................................................... ..........11-35
11.7.4.4 Ultra DMA Protocol ............... ...................................................................................... ............................11-35
11.8 ATA RESET/Power-Up ..................... .................................................................................... ..............................11-36
11.8.1 Hardware Reset ............................... .................................................................................... ............................11-36
11.8.2 Software Reset . ....................................................................................... ........................................................11-36
11.9 ATA I/O Cable Specifications ............................................................... ...............................................................11-37
Chapter 12 Universal Serial Bus (USB )
12.1 Overview ............................................................................ .....................................................................................12-1
12.2 Data Transfer Types .......... .................................................................................... ..................................................12-1
12.3 Host Controller Interface .................................... ....................................................................................... ..............12-2
12.3.1 Communication Channels ................................. .................................................................................... ............12-2
12.3.2 Data Structures ....................................... .................................................................................. .........................12-2
12.4 Host Control (HC) Operational Regis ters ............................................................................. ..................................12-5
12.4.1 Programming Note ............................................ .................................................................................. ..............12-5
12.4.2 Control and Status Partition—MBAR + 0x1000 ..............................................................................................12-6
12.4.2.1 USB HC Revision Register—MBAR + 0x1000 ........................................................................................12-6
12.4.2.2 USB HC Control Register—MBAR + 0x1004 ..........................................................................................12-6
12.4.2.3 USB HC Command Status Register—MBAR + 0x1008 ...........................................................................12-8
12.4.2.4 USB HC Interrupt Status Register —MBAR + 0x100C ...................... ......................................................12-9
12.4.2.5 USB HC Interrupt Enable Register—MBAR + 0x1010 .........................................................................12-10
12.4.2.6 USB HC Interrupt Disable Register—MBAR + 0x1014 ... ......................................................................12-11
12.4.3 Memory Pointer Partition—MBAR + 0x1018 ......................... ......................................................................12-12
12.4.3.1 USB HC HCCA Register—MBAR + 0x1018 .........................................................................................12-13