Main
Table of Contents
Chapter 1 Introduction
Chapter 2 Signal Descriptions
Chapter 3 Memory Map
Chapter 4 Resets and Reset Configuration
Chapter 5 Clocks and Power Management
Chapter 6 G2_LE Processor Core
Chapter 7 System Integration Unit (SIU)
Chapter 8 SDRAM Memory Controller
Chapter 9 LocalPlus Bus (External Bus Interface)
Chapter 10 PCI Controller
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Chapter 11 ATA Controller
Chapter 12 Universal Serial Bus (USB )
chapter 13 BestComm
Chapter 14 Fast Ethernet Controller (FEC)
Chapter 15 Programmable Serial Controllers (PSC)
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Chapter 16 XLB Arbiter
Chapter 17 Serial Peripheral Interface (SPI )
Chapter 18 Inter-Integrated Circuit (I 2C)
Chapter 19 Motorola Scalable CAN (MSCAN )
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Chapter 20 Byte Data Link Controller (BDLC)
Chapter 21 Debug Support and JTAG Interface
Appendix A Acronyms and Terms Appendix B List of Registers
List of Figures
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List of Tables
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Revision History
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Chapter 1 Introduction
1.1 Overview
1.1.1 Features
1.2 Architecture
Figure 1-1. Simplified Block DiagramMPC5200B
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1.2.1 Embedded e300 Core
MPC5200
1.2.2 BestComm I/ O Subsystem
1.2.2.1 Programmable Serial Controllers (PSCs)
1.2.2.2 10/100 Ethernet Controller
1.2.2.3 Universal Serial Bus (USB)
1.2.2.4 Infrared Support
1.2.4 Byte Data Link Controller - Digital BDLC-D
1.2.5 System Level Interfaces
1.2.5.1 Chip Selects
1.2.5.2 Interrupt Controller
1.2.5.3 Timers
1.2.6 SDRAM Controller and Interface
1.2.7 Multi-Function External LocalPlus Bus
1.2.8 Power Management
1.2.9 Systems Debug and Test
1.2.10 Physical Characteristics
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Chapter 2 Signal Descriptions
2.1 Overview
View Looking at Pins (Balls)
Figure 2-2. 272-Pin PBGA Top View
2.2 Pinout Tables
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Table2-2. Signals by Signal Name
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Freescale Semiconductor 2-13
Signal Name Ball/Pin Signal Name Ball/Pin
Table2-3. LocalPlus Bus Address / Data Pin Assignments
2-14 Freescale Semiconductor
Table2-4. LocalPlus Pin Functions
Freescale Semiconductor 2-15
Table2-4. LocalPlus Pin Functions (continued)
2-16 Freescale Semiconductor
Table2-5. LocalPlus Bus Address / Data Signals
Table2-4. LocalPlus Pin Functions (continued)
Freescale Semiconductor 2-17
2-18 Freescale Semiconductor
Freescale Semiconductor 2-19
2-20 Freescale Semiconductor
Freescale Semiconductor 2-21
2-22 Freescale Semiconductor
Freescale Semiconductor 2-23
2-24 Freescale Semiconductor
Freescale Semiconductor 2-25
2-26 Freescale Semiconductor
Freescale Semiconductor 2-27
Table2-6. PCI Dedicated Signals
2-28 Freescale Semiconductor
Table2-6. PCI Dedicated Signals (continued)
Freescale Semiconductor 2-29
Table2-7. ATA Dedicated Signals
Table2-6. PCI Dedicated Signals (continued)
2-30 Freescale Semiconductor
Table2-8. LocalPlus Dedicated Signals
Figure 2-4. PSC1 Port Map5 Pins Table2-9. PSC1 Pin Functions
45
55
GPIOAC971UART1(e) CODEC1
2-32 Freescale Semiconductor
Table2-10. PSC1 Functions by Pin
Freescale Semiconductor 2-33
Table2-10. PSC1 Functions by Pin (continued)
Figure 2-5. PSC2 Port Map5 Pins Table2-11. PSC2 Pin Functions
GPIOCAN1 /2CODEC2 AC972UART2(e)
55
45 4
Freescale Semiconductor 2-35
Table2-12. PSC2 Functions by Pin
2-36 Freescale Semiconductor
Table2-12. PSC2 Functions by Pin (continued)
Freescale Semiconductor 2-37
Figure 2-6. PSC3 Port Map10 Pins Table2-13. PSC3 Pin Functions
Pin name Dir. GPIO USB2 UART3 UART3e CODEC3
GPIOUSB2UART3(e ) CODEC3 SPI
1. If Soft Modem or RS-232 functionality is desired, use UARTe/CODEC function and use available
Table2-14. PSC3 Pin Functions (cont.)
Pin name Dir. CODEC3 w/ M SPI UART3 / SPI UART3e / SPI CODEC3 / SPI
Table2-15. PSC3 Functions by Pin
Freescale Semiconductor 2-39
2-40 Freescale Semiconductor
Freescale Semiconductor 2-41
2-42 Freescale Semiconductor
Figure 2-7. USB Port Map10 Pins
Freescale Semiconductor 2-43
USB Clock from PSC6 Port GPIO
USB Host RST_CFG
25
Table2-16. USB Pin Functions
Table2-17. USB Pin Functions by Pin
Freescale Semiconductor 2-45
Table2-17. USB Pin Functions by Pin (continued)
Figure 2-8. Ethernet Output Port Map8 Pins
2-46 Freescale Semiconductor
Table2-17. USB Pin Functions by Pin (continued)
Freescale Semiconductor 2-47
Figure 2-9. Ethernet Input / Control Port Map10 Pins Table2-18. Ethernet Pin Functions
GPIO
Function
ETH_8 ETH_9 ETH_10 ETH_11 ETH_12
ETH_13 ETH_14 ETH_15 ETH_16 ETH_17
Table2-19. Ethernet Pin Functions (cont.)
Table2-18. Ethernet Pin Functions (continued)
Freescale Semiconductor 2-49
Table2-20. Ethernet Output Functions by Pin
Table2-19. Ethernet Pin Functions (cont.)
2-50 Freescale Semiconductor
Freescale Semiconductor 2-51
2-52 Freescale Semiconductor
Freescale Semiconductor 2-53
2-54 Freescale Semiconductor
Freescale Semiconductor 2-55
2-56 Freescale Semiconductor
Notes:
Freescale Semiconductor 2-57
Table2-21. Ethernet Input / Control Functions by Pin
2-58 Freescale Semiconductor
Freescale Semiconductor 2-59
2-60 Freescale Semiconductor
Freescale Semiconductor 2-61
Figure 2-10. Timer Port Map8 Pins Table2-22. Timer Pin Functions
111
48
7
22
Table2-23. Timer Functions by Pin
2-64 Freescale Semiconductor
Table2-23. Timer Functions by Pin (continued)
Figure 2-11. PSC6 Port Map4 Pins
Freescale Semiconductor 2-65
Table2-23. Timer Functions by Pin (continued)
PSC6_0 PSC6_1 PSC6_2 PSC6_3
GPIO
Table2-24. PSC6 Pin Functions
Table2-25. PSC6 Functions by Pin
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Table2-27. SDRAM Bus P in Functions
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Table2-28. JTAG and Test Pin Functions
Table2-29. CLOCK / RESET Pin Functions
Table2-30. Dedicated GPIO Pin Function
Table2-31. Systems Integration Unit Pin Functions
Table2-31. Systems Integration Unit Pin Functions (continued)
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Chapter 3 Memory Map
3.1 Overview
3.2 Internal Register Memory Map
Table3-1 . Internal Register Memory Map
3.3 MPC5200B Memory Map
3.3.1 MPC5200B Internal Register Space
3.3.2 External Busses
3.3.2.1 SDRAM Bus
3.3.2.2 LocalPlus Bus
3.3.3 Memory Map Space Register Description
3.3.3.1 Memory Address Base Register MBAR + 0x0000
3.3.3.2 Boot and Chip Select Addresses
3.3.3.3 SDRAM Chip Select Configuration Registers
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3.3.3.4 IPBI Control Register and Wait State Enable MBAR+0x0054
Chapter 4 Resets and Reset Configuration
4.1 Overview
4.2 Hard and Soft Reset Pins
4.2.1 Power-On ResetPORRESET
4.2.2 Hard ResetHRESET
4.3 Reset Sequence
4.4 Reset Operation
PORRESET is negated and
4.5 Other Resets
4.6 Reset Configuration
Table4-2. Reset Configuration Word Source Pins
Table4-1. Module Specific Reset Signals (continued)
Table4-2. Reset Configuration Word Source Pins (continued)
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Chapter 5 Clocks and Power Management
5.1 Overview
5.2 Clock Distribution Module (CDM)
5.3 MPC5200B Clock Domains
Table5-1. Clock Distribution Module
Figure 5-1. Primary Synchronous Clock Domains
MPC5200B Clock Domains
Freescale Semiconductor 5-3
5.3.1 MPC5200B Top Level Clock Relations
e300
f
System APLL
Figure 5-2. MPC5200 Clock Relations
Table5-2. System PLL Ratios
Table5 -3. MPC5200B Clock Ratios
5.3.2 e300 Core Clock Domain
Table5-4. Typical System Clock Frequencies
Table5-5. e300 Core Frequencies vs. XLB Frequencies
Table5-6. e300 Core APLL Configuration Options
5.3.3 Processor Bus (XLB ) Clock Domain
5.3.4 SDRAM Memory Controller Clock Domain
Table5-6. e300 Core APLL Configuration Options (continued)
Figure 5-3. Timing DiagramClock Waveforms for SDRAM and DDR Memories
5.3.5 IPB Clock Domain
5.3.6 PCI Clock Domain
Table5-7. SDRA M Memory Controller Clock Domain
DDR SDRAM Memory Clocks
SDR SDRAM Memory Clocks
5.4 Power Management
5.4.1 Full-Power Mode
5.4.2 Power Conservation Modes
5.4.3 e300 Core Power Modes
5.4.3.1 Dynamic Power Mode
5.4.4 Deep-Sleep Mode
5.4.4.1 Entering Deep Sleep
5.4.4.2 Exiting Deep Sleep
5.5 CDM Registers
5-12 Freescale Semiconductor
CDM Registers
5.5.1 CDM JTAG ID Number RegisterMBAR + 0x0200
Device I.D. Register = 1001 101D hex
5.5.2 CDM Power On Reset Configuration RegisterMBAR + 0x0204
This is a mostly read-only register containing the configuration value latched at POR.
Table5-8. CDM JTAG ID Number Register
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5.5.3 CDM Bread Crumb RegisterMBAR + 0x0208
5.5.4 CDM Configuration RegisterMBAR + 0x020C
Table5-10. CDM Bread Crumb Register
Table5-11. CDM Configuration Register
5.5.5 CDM 48MHz Fractional Divider Configuration RegisterMBAR + 0x0210
Table5-12. CDM 48MHz Fractional Divider Configuration Register
5.5.6 CDM Clock Enable RegisterMBAR + 0x0214
Table5-13. CDM Clock Enable Register
5.5.7 CDM System Oscillator Configuration RegisterMBAR + 0x0218
Table5 -14. CDM System Oscillator Configuration Register
5.5.8 CDM Clock Control Sequencer Configuration RegisterMBAR + 0x021C
Table5-15. CDM Clock Control Sequencer Configuration Register
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5.5.9 CDM Soft Reset RegisterMBAR + 0x0220
5.5.10 CDM System PLL Status RegisterMBAR + 0x0224
Table5 -16. CDM Soft Reset Register
Table5-17. CDM System PLL Status Register
5.5.11 PSC1 Mclock Config RegisterMBAR + 0x0228
Table5-18. CDM PSC1 Mclock Config
5.5.12 PSC2 Mclock Config RegisterMBAR + 0x022C
5.5.13 PSC3 Mclock Config RegisterMBAR + 0x0230
Table5-19. CDM PSC2 Mclock Config
Table5-20. CDM PSC3 Mclock Config
5.5.14 PSC6 (IrDA) Mclock Config RegisterMBAR + 0x0234
Table5-21. CDM PSC6 Mclock Config
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Chapter 6 e300 Processor Core
6.1 Overview
6.2 MPC5200B e300 Processor Core Functional Overview
Table6-1. SVR Values
6.3 e300 Core Reference Manual
6.4 Not supported e300 Core Features
6.4.1 Not supported instruction
6.4.2 Not supported XLB parity feature
Chapter 7 System Integration Unit (SIU )
7.1 Overview
7.2 Interrupt Controller
7.2.1 Block Description
Table7-1. Interrupt Sources
7.2.1.1 Machine Check Pincore_mcp
7.2.1.2 System Management Interruptcore_smi
7.2.1.3 Standard Interruptcore_int
Table7-2. System Management Interrupt Pin Interrupts
Table7-3. e300 core Interrupt Pins Summary
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7.2.2 Interface Description
Figure 7-2. Interrupt Controller Routing Scheme
7.2.3 Programming Note
7.2.4 Interrupt Controller Registers
7.2.4.1 ICTL Peripheral Interrupt Mask RegisterMBAR + 0x0500
Table7-4. ICTL Peripheral Interrupt Mask Register
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7.2.4.2 ICTL Peripheral Priority and HI/ LO Select 1 Register MBAR + 0x0504
7.2.4.3 ICTL Peripheral Priority and HI/ LO Select 2 Register MBAR + 0x0508
7.2.4.4 ICTL Peripheral Priority and HI/ LO Select 3 Register MBAR + 0x050C
Table7-6 . ICTL Peripheral Priority and HI/LO Select 2 Register
Table7-7. ICTL Peripheral Priority and HI/ LO Select 3 Register
7.2.4.5 ICTL External Enable and External Types Register MBAR + 0x0510
Table7-8. ICTL External Enable and External Types Register
7.2.4.6 ICTL Critical Priority and Main Interrupt Mask RegisterMBAR + 0x0514
Table 7-9. ICTL Critical Priority and Main Interrupt Mask Register)
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7.2.4.7 ICTL Main Interrupt Priority and INT /SMI Select 1 Register MBAR + 0x0518
7.2.4.8 ICTL Main Interrupt Priority and INT /SMI Select 2 RegisterMBAR + 0x051C
7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded RegisterMBAR + 0x0524
Table7-1 2. ICTL PerStat, MainStat, CritStat Encoded Register
7.2.4.10 ICTL Critical Interrupt Status All RegisterMBAR + 0x0528
Table7-1 3. ICTL Critical Interrupt Status All Register
7.2.4.11 ICTL Main Interrupt Status All RegisterMBAR + 0x052C
Register Table7-1 4. ICTL Main Interrupt Status All Register
22 MSa7
7.2.4.12 ICTL Peripheral Interrupt Status All RegisterMBAR + 0x0530
Table7-15. ICTL Peripheral Interrupt Status All Register
7.2.4.13 ICTL Peripheral Interrupt Status All RegisterMBAR + 0x0538
Table7-16. ICTL Bus Error Status Register
7.2.4.14 ICTL Main Interrupt Emulation All RegisterMBAR + 0x0540
7.2.4.15 ICTL Peripheral Interrupt Emulation All RegisterMBAR + 0x0544
7.2.4.16 ICTL IRQ Interrupt Emulation All RegisterMBAR + 0x0548
Table7-1 9. ICTL IRQ Interrupt Emulation All Register
7.3 General Purpose I /O (GPIO )
Table 7-20. GPIO Pin List
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Table7-20. GPIO Pin List (continued)
7.3.1 GPIO Pin Multiplexing
Figure 7-3. GPIO/Gener ic MUX Cell
Pin MUX Logic
I/O Cell
7.3.1.1 PSC1 ( UART1/AC97/ CODEC1)
7.3.1.2 PSC2 ( CAN1/2/UART2/AC97/ CODEC2)
7.3.1.3 PSC3 ( USB2/CODEC3 /SPI/UART3)
7.3.1.4 USB1/RST_CONFIG
7.3.1.5 Ethernet/USB2 /UART4/5/J1850/RST_CONFIG
7.3.1.6 PSC6
7.3.1.7 I2C
7.3.1.8 GPIO Timer Pins
7.3.1.9 Dedicated GPIO Port
7.3.2 GPIO Programmers Model
7.3.2.1 GPIO Standard RegistersMBAR+ 0x0B00
7.3.2.1.1 GPS Port Configuration RegisterMBAR + 0x0B00
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7.3.2.1.2 GPS Simple GPIO Enables RegisterMBAR + 0x0B04
Table7- 22. GPS Simple GPIO Enables Register
7.3.2.1.3 GPS Simple GPIO Open Drain Type Register MBAR + 0x0B08
Table7-23. GPS Simple GPIO Open Drain Type Register
7.3.2.1.4 GPS Simple GPIO Data Direction RegisterMBAR + 0x0B0C
Table7-2 4. GPS Simple GPIO Data Direction Register
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7.3.2.1.5 GPS Simple GPIO Data Output Values Register MBAR + 0x0B10
7.3.2.1.6 GPS Simple GPIO Data Input Values Register MBAR + 0x0B14
Table7-26. GPS Simple GPIO Data Input Values Register
7.3.2.1.7 GPS GPIO Output-Only Enables Register MBAR + 0x0B18
Table7-27. GPS GPIO Output-Only Enables Register
7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register MBAR + 0x0B1C
Table7 -28. GPS GPIO Output-Only Data Value Out Register
7.3.2.1.9 GPS GPIO Simple Interrupt Enable RegisterMBAR + 0x0B20
Table 7-29. GPS GPIO Simple Interrupt Enables Register
7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register MBAR + 0x0B24
Table 7-30. GPS GPIO Simple Interrupt Open-Drain Emulation Register
7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register MBAR + 0x0B28
7.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register MBAR + 0x0B2C
Table 7-31. GPS GPIO Simple Interrupt Data Direction Register
Table7-3 2. GPS GPIO Simple Interrupt Data Value Out Register
7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register MBAR + 0x0B30
Table7-33. GPS GPIO Simple Interrupt Interrupt Enable Register
7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register MBAR + 0x0B34
7.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register MBAR + 0x0B38
Table7-3 4. GPS GPIO Simple Interrupt Interrupt Types Register
Table7- 35. GPS GPIO Simple Interrupt Master Enable Register
7.3.2.1.16 GPS GPIO Simple Interrupt Status RegisterMBAR + 0x0B3C
Table7-36. GPS GPIO Simple Interrupt Status Register
7.3.2.2 WakeUp GPIO RegistersMBAR+ 0x0C00
7.3.2.2.1 GPW WakeUp GPIO Enables RegisterMBAR + 0x0C00
Table7 -37. GPW WakeUp GPIO Enables Register
7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register MBAR + 0x0C04
7.3.2.2.3 GPW WakeUp GPIO Data Direction RegisterMBAR + 0x0C08
Table7-38. GPW WakeUp GPIO Open Drain Emulation Register
Table7 -39. GPW WakeUp GPIO Data Direction Register
7.3.2.2.4 GPW WakeUp GPIO Data Value Out Register MBAR + 0x0C0C
Table7-40. GPW WakeUp GPIO Data Value Out Register
7.3.2.2.5 GPW WakeUp GPIO Interrupt Enable RegisterMBAR + 0x0C10
7.3.2.2.6 GPW WakeUp GPIO Individual Interrupt Enable Register MBAR + 0x0C14
Table7-41. GPW WakeUp GPIO Interrupt Enable Register
Table7-42. GPW WakeUp GPIO Individual Interrupt Enable Register
7.3.2.2.7 GPW WakeUp GPIO Interrupt Types RegisterMBAR + 0x0C18
Table7-43. GPW WakeUp GPIO Interrupt Types Register
7.3.2.2.8 GPW WakeUp GPIO Master Enables Register MBAR + 0x0C1C
Table7-44. GPW WakeUp GPIO Master Enables Register
7.3.2.2.9 GPW WakeUp GPIO Data Input Values Register MBAR + 0x0C20
Table7-45. GPW WakeUp GPIO Data Input Values Register
7.3.2.2.10 GPW WakeUp GPIO Status RegisterMBAR + 0x0C24
7.4 General Purpose Timers ( GPT)
7.4.1 Timer Configuration Method
7.4.2 Mode Overview
7.4.3 Programming Notes
7.4.4 GPT RegistersMBAR + 0x0600
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7.5 Slice Timers
7.5.1 SLT RegistersMBAR + 0x0700
7.5.1.1 SLT 0 Terminal Count RegisterMBAR + 0x0700 SLT 1 Terminal Count RegisterMBAR + 0x0710
7.5.1.2 SLT 0 Control RegisterMBAR + 0x0704 SLT 1 Control RegisterMBAR + 0x0714
Table7-51. SLT 0 Terminal Count Register SLT 1 Terminal Count Register
Table7-52. SLT 0 Control Register SLT 1 Control Register
7.5.1.3 SLT 0 Count Value RegisterMBAR + 0x0708 SLT 1 Count Value RegisterMBAR + 0x0718
Table7-53. SLT 0 Count Value Register SLT 1 Count Value Register
7.5.1.4 SLT 0 Timer Status RegisterMBAR + 0x070C SLT 1 Timer Status RegisterMBAR + 0x071C
7.6 Real-Time Clock
Table 7-54. SLT 0 Timer Status Register SLT 1 Timer Status Register
7.6.1 Real-Time Clock Signals
7.6.2 Programming Note
7.6.3 RTC Interface RegistersMBAR + 0x0800
7.6.3.1 RTC Time Set RegisterMBAR + 0x0800
Table7-56. RTC Time Set Register
7.6.3.2 RTC Date Set RegisterMBAR + 0x0804
Table7-57. RTC Date Set Register
7.6.3.3 RTC New Year and Stopwatch RegisterMBAR + 0x0808
7.6.3.4 RTC Alarm and Interrupt Enable RegisterMBAR + 0x080C
Table7-58. RTC New Year and Stopwatch Register
0:6
Table7-59. RTC Alarm and Interrupt Enable Register
7.6.3.5 RTC Current Time RegisterMBAR + 0x0810
Table7-60. RTC Current Time Register
7.6.3.6 RTC Current Date RegisterMBAR + 0x0814
7.6.3.7 RTC Alarm and Stopwatch Interrupt RegisterMBAR + 0x0818
Table7-61. RTC Current Date Register
Table7-62. RTC Alarm and Stopwatch Interrupt Register
7.6.3.8 RTC Periodic Interrupt and Bus Error RegisterMBAR + 0x081C
Table7-63. RTC Periodic Interrupt and Bus Error Register
7.6.3.9 RTC Test Register/Divides RegisterMBAR + 0x0820
Table7 -64. RTC Test Register/Divides Register
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Chapter 8 SDRAM Memory Controller
8.1 Overview
8.2 Terminology and Notation
8.2.1 Endian-ness
8.3 Features
8.3.1 Devices Supported
Table8-1. 32-Bit External Data Width Legal Memory Configurations
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Table8-2. 16-Bit External Data Width Legal Memory Configurations
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8-14 Freescale Semiconductor
Figure 8-1. Block DiagramSDRAM Subsystem Example
8.4 Functional Description
8.4.1 External Signals (SDRAM Side)
Table8-3. SDRAM External Signals
8.4.2 Block Diagram
8.4.3 Transfer Size
SDRAM Memory Controller
External Interface
Internal XL bus
8.4.4 Commands
8.4.4.1 Load Mode/Extended Mode Register Command
Table8-4. SDRAM Commands
8.4.4.2 Precharge All Banks Command
8.4.4.3 Row and Bank Active Command
8.4.4.4 Read Command
8.4.4.5 Write Command
8.4.4.6 Burst Terminate Command
8.5 Operation
8.5.1 Power-Up Initialization
8.5.2 Read Clock
8.6 Programming the SDRAM Controller
8.7 Memory Controller Registers (MBAR+0x0100:0x010C)
8.7.1 Mode RegisterMBAR + 0x0100
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8.7.2 Control RegisterMBAR + 0x0104
Table8-7. High Address Usage
Table8 -8. 32-Bit SDRAM Address Multiplexing Device Structure
Row bits Col bits Bank bits
hi_ addr
Internal XLA[4:29] 456789:19 20:21 22:29
8.7.3 Configuration Register 1MBAR + 0x0108
Table8 -9. 16-Bit SDRAM Address Multiplexing Device Structure
Row bits Col bits Bank bits
hi_ addr
Internal XLA[4:30] 456789:19 20:21 22:30
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8.7.4 Configuration Register 2MBAR + 0x010C
Table8-11. Memory Controller Configuration Register 2
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Figure 8-3. Programmable Command Timings
8-30 Freescale Semiconductor
Address Bus Mapping
8.8 Address Bus Mapping
Figure 8-4. Address Bus Mapping (32-Bit External Data Width)
Figure 8-5. Address Bus Mapping (16-Bit External Data Width)
8.8.1 ExamplePhysical Address Multiplexing
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Chapter 9 LocalPlus Bus (External Bus Interface)
9.1 Overview
9.2 Features
9.3 Interface
9.3.1 External Signals
Table 9-1. LocalPlus External Signals
9.3.2 Block Diagram
Registers
LPC
IPBI
Figure 9-1. LPC Concept Diagram
9.4 Modes of Operation
Figure 9-3. Output Enable Signal
9.4.1 Non-MUXed Mode
MPC5200
LPC Interface
Table9-2. Non-Muxed Mode Options
Table9-3. Non-Muxed Aligned Data Transfers
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9.4.2 MUXed Mode
Table9-4. MUXed Mode Options
9.4.2.1 Address Tenure
9.4.2.2 Data Tenure
Table 9-5. Muxed Aligned Data Transfers
9.5 Configuration
9.5.2 Chip Selects Configuration
9.5.3 Reset Configuration
9.6 DMA (BestComm) Interface (SCLPC)
9.7 Programmers Model
9.7.1 Chip Select/LPC RegistersMBAR + 0x0300
Table9-6. BOOT_CONFIG (RST_CONFIG) Options
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9.7.1.1 Chip Select 0/Boot Configuration RegisterMBAR + 0x0300
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9.7.1.3 Chip Select Control RegisterMBAR + 0x0318
Table9-9. Chip Select Control Register
9.7.1.4 Chip Select Status RegisterMBAR + 0x031C
9.7.1.5 Chip Select Burst Control RegisterMBAR + 0x0328
Table 9-10. Chip Select Status Register
Table9-11. Chip Select Burst Control Register
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9.7.1.6 Chip Select Deadcycle Control RegisterMBAR + 0x032C
Table9-12. Chip Select Deadcycle Control Register
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9.7.2 SCLPC RegistersMBAR + 0x3C00
9.7.2.1 SCLPC Packet Size RegisterMBAR + 0x3C00
Table9-13. SCLPC Packet Size Register
9.7.2.2 SCLPC Star t Address RegisterMBAR + 0x3C04
9.7.2.3 SCLPC Control RegisterMBAR + 0x3C08
Table9-14. SCLPC Start Address Register
Table9-15. SCLPC Control Register
9.7.2.4 SCLPC Enable RegisterMBAR + 0x3C0C
Table9 -16. SCLPC Enable Register
9.7.2.5 SCLPC Bytes Done Status RegisterMBAR + 0x3C14
Table9-17. SCLPC Bytes Done Status Register
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9.7.3 SCLPC FIFO RegistersMBAR + 0x3C40
9.7.3.1 LPC Rx /Tx FIFO Data Word RegisterMBAR + 0x3C40 LPC_rx/tx_fifo_data_word_register
Table 9-18. LPC Rx/Tx FIFO Data Word Register
9.7.3.2 LPC Rx /Tx FIFO Status RegisterMBAR + 0x3C44
Table9-19. LPC Rx /Tx FIFO Status Register
9.7.3.3 LPC Rx /Tx FIFO Control RegisterMBAR + 0x3C48
9.7.3.4 LPC Rx /Tx FIFO Alarm RegisterMBAR + 0x3C4C
Table9-20. LPC Rx /Tx FIFO Control Register
Table9-21. LPC Rx /Tx FIFO Alarm Register
9.7.3.5 LPC Rx /Tx FIFO Read Pointer RegisterMBAR + 0x3C50
9.7.3.6 LPC Rx /Tx FIFO Write Pointer RegisterMBAR + 0x3C54
Table9-22. LPC Rx /Tx FIFO Read Pointer Register
Table9-23. LPC Rx /Tx FIFO Write Pointer Register
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Chapter 10 PCI Controller
10.1 Overview
10.1.1 Features
10.1.2 Block Diagram
PCI Controller Block
External PCI bus
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10.3 Registers
Table10-2. PCI Register Map
Table10-3. PCI Communication System Interface Register Map
Table10-2. PCI Register Map (continued)
10.3.1 PCI Controller Type 0 Configuration Space
Table10-3. PCI Communication System Interface Register Map (continued)
10.3.1.1 Device ID/ Vendor ID Registers PCIIDR(R) MBAR + 0x0D00
10.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) MBAR + 0x0D04
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10.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) MBAR + 0x0D08
10.3.1.4 Configuration 1 Register PCICR1(R/RW) MBAR + 0x0D0C
10.3.1.5 Base Address Register 0 PCIBAR0(RW) MBAR + 0x0D10
10.3.1.6 Base Address Register 1 PCIBAR1(RW) MBAR + 0x0D14
10.3.1.7 CardBus CIS Pointer Register PCICCPR(RW) MBAR + 0x0D28
10.3.1.8 Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)MBAR + 0x0D2C
10.3.1.9 Expansion ROM Base Address PCIERBAR(R) MBAR + 0x0D30
10.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)MBAR + 0x0D34
10.3.2 General Control/Status Registers
Page
Page
10.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) MBAR + 0x0D64
10.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) MBAR + 0x0D68
10.3.2.4 Target Control Register PCITCR(RW) MBAR + 0x0D6C
10.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)MBAR + 0x0D70
10.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) MBAR + 0x0D74
Table 1.
10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) MBAR + 0x0D78
10.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) MBAR + 0x0D80
10.3.2.9 Initiator Control Register PCIICR(RW) MBAR + 0x0D84
10.3.2.10 Initiator Status Register PCIISR(RWC) MBAR + 0x0D88
10.3.2.11 PCI Arbiter Register PCIARB(RW) MBAR + 0x0D8C
10.3.2.12 Configuration Address Register PCICAR (RW) MBAR + 0x0DF8
10.3.3 Communication Sub-System Interface Registers
10.3.3.1 Multi-Channel DMA Transmit Interface
10.3.3.1.1 Tx Packet Size PCITPSR(RW) MBAR + 0x3800
10.3.3.1.2 Tx Start Address PCITSAR(RW) MBAR + 0x3804
10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) MBAR + 0x3808
Page
10.3.3.1.4 Tx Enables PCITER(RW)MBAR + 0x380C
10.3.3.1.5 Tx Next Address PCITNAR(R) MBAR + 0x3810
10.3.3.1.6 Tx Last Word PCITLWR(R) MBAR + 0x3814
10.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) MBAR + 0x3818
10.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) MBAR + 0x3820
10.3.3.1.9 Tx Status PCITSR(RWC) MBAR + 0x381C
10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) MBAR + 0x3840
10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) MBAR + 0x3844
10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) MBAR + 0x3848
10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) MBAR + 0x384C
Page
10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) MBAR + 0x3850
10.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) MBAR + 0x3854
10.3.3.2 Multi-Channel DMA Receive Interface
10.3.3.2.1 Rx Packet Size PCIRPSR(RW) MBAR + 0x3880
10.3.3.2.2 Rx Start Address PCIRSAR (RW) MBAR + 0x3884
10.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) MBAR + 0x3888
Page
10.3.3.2.4 Rx Enables PCIRER (RW) MBAR + 0x388C
10.3.3.2.5 Rx Next Address PCIRNAR(R) MBAR + 0x3890
10.3.3.2.6 Rx Last Word PCIRLWR(R) MBAR + 0x3894
10.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) MBAR + 0x3898
10.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) MBAR + 0x38A0
10.3.3.2.9 Rx Status PCIRSR (R/sw1) MBAR + 0x389C
10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) MBAR + 0x38C0
10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) MBAR + 0x38C4
10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) MBAR + 0x38C8
10.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) MBAR + 0x38CC
10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) MBAR + 0x38D0
10.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) MBAR + 0x38D4
10.4 Functional Description
10.4.1 PCI Bus Protocol
10.4.1.1 PCI Bus Background
10.4.1.2 Basic Transfer Control
Table10-4. PCI Command encoding
Page
Page
10.4.1.5 Addressing
10.4.1.5.1 Memory space addressing
Table10-5. PCI Bus Commands (continued)
10.4.1.5.2 I/O space addressing
10.4.1.5.3 Configuration space addressing and transactions
Table10 -6. PCI I/O space byte decoding
10.4.1.5.4 Address decoding
Reserved
10.4.2 Initiator Arbitration
Figure 10-6. Initiator Arbitration Block Diagram
10.4.2.1 Priority Scheme
10.4.3 Configuration Interface
10.4.4 XL bus Initiator Interface
10.4.4.1 Endian Translation
Page
10.4.4.2 Configuration Mechanism
10.4.4.2.1 Type 0 Configuration Translation
Page
10.4.4.2.2 Type 1 Configuration Translation
10.4.4.2.3 Interrupt Acknowledge Transactions
10.4.4.2.4 Special Cycle Transactions
Table10-8. Type 0 Configuration Device Number to IDSEL Translation (continued)
10.4.4.3 Transaction Termination
10.4.5 XL bus Target Interface
Table 10-9. Special Cycle Message Encodings
Table10-10. Unsupported XL Bus Transfers
10.4.5.1 Reads from Local Memory
10.4.5.2 Local Memory Writes
10.4.5.3 Data Translation
Table10-11. Aligned PCI to XL bus Transfers
10.4.5.4 Target Abort
10.4.6 Communication Sub-System Initiator Interface
Table10-12. Non-contiguous PCI to XL bus Transfers (require two XL Bus bus accesses)
10.4.6.1 Access Width
10.4.6.2 Addressing
ferent as explained in Section 10.4.1.5, Addressing.
10.4.6.3 Data Translation
10.4.6.4 Initialization
10.4.6.5 Restart and Reset
10.4.6.6 PCI Commands
10.4.6.7 FIFO Considerations
10.4.6.8 Alarms
10.4.6.9 Bus Errors
10.5 PCI Arbiter
Table1 0-14. XL Bus:IP:PCI Clock Ratios
10.6 Application Information
10.6.1 XL bus Initiated Transaction Mapping
Table10-15. Transaction Mapping: XL Bus -> PCI
10.6.2 Address Maps
10.6.2.1 Address Translation
10.6.2.1.1 Inbound Address Translation
Table10-15. Transaction Mapping: XL Bus -> PCI (continued)
Figure 10-8. Inbound Address Map
10.6.2.1.2 Outbound Address Translation
Figure 10-9. Outbound Address Map
10.6.2.1.3 Base Address Register Overview
10.6.3 XL bus Arbitration Priority
Page
Chapter 11 ATA Controller
11.1 Overview
PCI Handshake
Local Bus
Figure 11-1. ATA Controller Interface
11.3 ATA Register Interface
11.3.1 ATA Host RegistersMBAR + 0x3A00
11.3.1.1 ATA Host Configuration RegisterMBAR + 0x3A00
Table11-1. ATA Host Configuration Register
11.3.1.2 ATA Host Status RegisterMBAR + 0x3A04
11.3.1.3 ATA PIO Timing 1 RegisterMBAR + 0x3A08
Table11-2. ATA Host Status Register
Table11-3. ATA PIO Timing 1 Register
11.3.1.4 ATA PIO Timing 2 RegisterMBAR + 0x3A0C
11.3.1.5 ATA Multiword DMA Timing 1 RegisterMBAR + 0x3A10
Table11-4. ATA PIO Timing 2 Register
Table1 1-5. ATA Multiword DMA Timing 1 Register
11.3.1.6 ATA Multiword DMA Timing 2 RegisterMBAR + 0x3A14
11.3.1.7 ATA Ultra DMA Timing 1 RegisterMBAR + 0x3A18
Table1 1-6. ATA Multiword DMA Timing 2 Register
Table11-7. ATA Ultra DMA Timing 1 Register
11.3.1.8 ATA Ultra DMA Timing 2 RegisterMBAR + 0x3A1C
11.3.1.9 ATA Ultra DMA Timing 3 RegisterMBAR + 0x3A20
Table11-8. ATA Ultra DMA Timing 2 Register
Table11-9. ATA Ultra DMA Timing 3 Register
11.3.1.10 ATA Ultra DMA Timing 4 RegisterMBAR + 0x3A24
Table11-10. ATA Ultra DMA Timing 4 Register
11.3.1.11 ATA Ultra DMA Timing 5 RegisterMBAR + 0x3A28
11.3.1.12 ATA Share Count RegisterMBAR + 0x3A2C
11.3.2 ATA FIFO RegistersMBAR + 0x3A00
Table11-11. ATA Ultra DMA Timing 5 Register
Table11-12. ata_shre_cnt
11.3.2.1 ATA Rx/Tx FIFO Data Word RegisterMBAR + 0x3A3C
11.3.2.2 ATA Rx/Tx FIFO Status RegisterMBAR + 0x3A40
Table11-13. ATA Rx/Tx FIFO Data Word Register
Table11-14. ATA Rx/Tx FIFO Status Register
11.3.2.3 ATA Rx/Tx FIFO Control RegisterMBAR + 0x3A44
11.3.2.4 ATA Rx/Tx FIFO Alarm RegisterMBAR + 0x3A48
Table1 1-15. ATA Rx /Tx FIFO Control Register
Table11-16. ATA Rx/Tx FIFO Alarm Register
11.3.2.5 ATA Rx/Tx FIFO Read Pointer RegisterMBAR + 0x3A4C
11.3.2.6 ATA Rx/Tx FIFO Write Pointer RegisterMBAR + 0x3A50
Table 11-17. ATA Rx /Tx FIFO Read Pointer Register
Table11-18. ATA Rx/Tx FIFO Write Pointer Register
11.3.3 ATA Drive RegistersMBAR + 0x3A00
11.3.3.1 ATA Drive Device Control RegisterMBAR + 0x3A5C
Table11-19. ATA Drive Device Control Register
11.3.3.2 ATA Drive Alternate Status RegisterMBAR + 0x3A5C
11.3.3.3 ATA Drive Data RegisterMBAR + 0x3A60
Table1 1-20. ATA Drive Al ternate Status Register
Table1 1-21. ATA Drive D ata Register
11.3.3.4 ATA Drive Features RegisterMBAR + 0x3A64
11.3.3.5 ATA Drive Error RegisterMBAR + 0x3A64
Table11-22. ATA Drive Features Register
Table11-23. ATA Drive Error Register
11.3.3.6 ATA Drive Sector Count RegisterMBAR + 0x3A68
11.3.3.7 ATA Drive Sector Number RegisterMBAR + 0x3A6C
Table11-24. ATA Drive Sector Count Register
Table11-25. ATA Drive Sector Number Register
11.3.3.8 ATA Drive Cylinder Low RegisterMBAR + 0x3A70
11.3.3.9 ATA Drive Cylinder High RegisterMBAR + 0x3A74
Table11-26. ATA Drive Cylinder Low Register
Table11-27. ATA Drive Cylinder High Register
11.3.3.10 ATA Drive Device /Head RegisterMBAR + 0x3A78
11.3.3.11 ATA Drive Device Command RegisterMBAR + 0x3A7C
Table11-28. ATA Drive Device/Head Register
0
Table1 1-29. ATA Drive Device Comma nd Register
Page
11.3.3.12 ATA Drive Device Status RegisterMBAR + 0x3A7C
11.4 ATA Host Controller Operation
11.4.1 PIO State Machine
Table11-31. PIO Timing Requirements
11.4.2 DMA State Machine
11.4.2.1 Software Requirements
Table11-32. Multiword DMA Timing Requirements
Table11-31. PIO Timing Requirements (continued)
11.5 Signals and Connections
Table1 1-33. MPC5200B External Signals
Figure 11-2. ConnectionsController Cable, System Board, MPC5200B
LEGEND
11.6 ATA Interface Description
Table11-34. ATA Controller External Connections
Bidirectional Output Input
MPC5200
See Notes
Table11-34. ATA Controller External Connections (continued)
11-26 Freescale Semiconductor
ATA Bus Background
Figure 11-3. Pin DescriptionATA Interface
D E V I C E
11.7 ATA Bus Background
11.7.1 Terminology
11.7.2 ATA Modes
11.7.3 ATA Addressing
Table1 1-35. ATA Standards
Table11-36. ATA Physical Level Modes
11.7.3.1 ATA Register Addressing
11.7.3.2 Drive Interrupt
11.7.3.3 Sector Addressing
Table11-37. ATA Register Address/Chip Select Decoding
11.7.3.4 Physical /Logical Addressing Modes
Figure 11-4. ATA Sector Format
11.7.4 ATA Transactions
11.7.4.1 PIO Mode Transactions
11.7.4.1.1 Class 1PIO Read
Figure 11-5. Timing DiagramPIO Read Command (Class 1)
11.7.4.1.2 Class 2PIO Write
Figure 11-6. Timing DiagramPIO Write Command (Class 2)
11.7.4.1.3 Class 3Non-Data Command
Figure 11-7. Timing DiagramNon-Data Command (Class 3)
11.7.4.2 DMA Protocol
Table11-38. DMA Command Parameters
11-34 Freescale Semiconductor
ATA Bus Background
Figure 11-8. Flow DiagramDMA Command Protocol
11.7.4.3 Multiword DMA Transactions
11.7.4.3.1 Class 4DMA Command
Figure 11-9. Timing DiagramDMA Command (Class 4)
11.7.4.4 Ultra DMA Protocol
11.8 ATA RESET /Power-Up
11.8.1 Hardware Reset
11.8.2 Software Reset
Table11-39. Redefinition of Signal Lines for Ultra DMA Protocol
11.9 ATA I/O Cable Specifications
Page
Chapter 12 Universal Serial Bus (USB )
12.1 Overview
12.2 Data Transfer Types
12.3 Host Controller Interface
12.3.1 Communication Channels
OpenHCI
Figure 12-2. Communication Channels
12.3.2 Data Structures
Figure 12-4. Interrupt ED Structure
Interrupt Endpoint Descriptor Placeholder
Endpoint Poll Interval (ms)
Interrupt Headpointers
Figure 12-5. Sample Interrupt Endpoint Schedule
12.4 Host Control (HC) Operational Registers
Endpoint Poll Interval (ms)
12.4.1 Programming Note
Interrupt Endpoint Descriptor Interrupt Headpointers
12.4.2 Control and Status PartitionMBAR + 0x1000
12.4.2.1 USB HC Revision RegisterMBAR + 0x1000
12.4.2.2 USB HC Control RegisterMBAR + 0x1004
Table12-1. USB HC Revision Register
Table12-2. USB HC Control Register
Page
12.4.2.3 USB HC Command Status RegisterMBAR + 0x1008
Table12-3. USB HC Command Status Register
12.4.2.4 USB HC Interrupt Status Register MBAR + 0x100C
Table12-4. USB HC Interrupt Status Register
12.4.2.5 USB HC Interrupt Enable RegisterMBAR + 0x1010
Table12-5. USB HC Interrupt Enable Register
12.4.2.6 USB HC Interrupt Disable RegisterMBAR + 0x1014
Table12-6. USB HC Interrupt Disable Register
12.4.3 Memor y Pointer PartitionMBAR + 0x1018
12.4.3.1 USB HC HCCA RegisterMBAR + 0x1018
12.4.3.2 USB HC Period Current Endpoint Descriptor Register MBAR + 0x101C
Table12-7. USB HC HCCA Register
Table12-8. USB HC Period Current Endpoint Descriptor Register
12.4.3.3 USB HC Control Head Endpoint Descriptor Register MBAR + 0x1020
12.4.3.4 USB HC Control Current Endpoint Descriptor Register MBAR + 0x1024
12.4.3.5 USB HC Bulk Head Endpoint Descriptor RegisterMBAR + 0x1028
Table12-9. USB HC Control Head Endpoint Descriptor Register
Table12-10. USB HC Control Current Endpoint Descriptor Register
12.4.3.6 USB HC Bulk Current Endpoint Descriptor RegisterMBAR + 0x102C
12.4.3.7 USB HC Done Head RegisterMBAR + 0x1030
Table12-11. USB HC Bulk Head Endpoint Descriptor Register
Table12-12. USB HC Bulk Current Endpint Descriptor Register
12.4.4 Frame Counter PartitionMBAR + 0x1034
12.4.4.1 USB HC Frame Interval RegisterMBAR + 0x1034
Table12-13. USB HC Done Head Register
Table12-14. USB HC Frame Interval Register
12.4.4.2 USB HC Frame Remaining RegisterMBAR + 0x1038
12.4.4.3 USB HC Frame Number RegisterMBAR + 0x103C
Table12-15. USB HC Frame Remai ning Register
Table12-16. USB HC Frame Number Register
12.4.4.4 USB HC Periodic Start RegisterMBAR + 0x1040
12.4.4.5 USB HC LS Threshold RegisterMBAR + 0x1044
Table12-17. USB HC Periodic Start Register
Table12-18. USB HC LS Threshold Register
12.4.5 Root Hub PartitionMBAR + 0x1048
12.4.5.1 USB HC Rh Descriptor A RegisterMBAR + 0x1048
Table12-19. USB HC Rh Descriptor A Register
12.4.5.2 USB HC Rh Descriptor B RegisterMBAR + 0x104C
12.4.5.3 USB HC Rh Status RegisterMBAR + 0x1050
Table12-20. USB HC Rh Descriptor B Register
Table12-21. USB HC Rh Status R egister
12.4.5.4 USB HC Rh Port1 Status RegisterMBAR + 0x1054
Page
Page
Page
12.4.5.5 USB HC Rh Port2 Status RegisterMBAR + 0x1058
Table12-23. USB HC Rh Port2 Status Register
Page
Page
Page
Page
Chapter 13 BestComm
13.1 Overview
13.2 BestComm Functional Description
13.3 Features summary
13.4 Descriptors
13.5 Tasks
13.6 Memory Map/ Register Definitions
13.7 Task Table (Entry Table)
13.8 Task Descriptor Table
13.9 Variable Table
13.10 Function Descriptor Table
13.11 Context Save Area
13.14 BestComm XLB Address Snooping
13.15 BestComm DMA RegistersMBAR+0x1200
13.15.1 SDMA Task Bar RegisterMBA R + 0x1200 sdma_task_bar_register
Table13-1. SDMA Task Bar Register
13.15.2 SDMA Current Pointer RegisterMBAR + 0x1204
13.15.3 SDMA End Pointer RegisterMBAR + 0x1208
13.15.4 SDMA Variable Pointer RegisterMBAR + 0x120C
Table13-2. SDMA Current Pointer Register
Table13-3. SDMA End Pointer Register
13.15.5
SDMA Interrupt Vector, PTD Control Register
MBAR + 0x1210
Table13 -5. SDMA Interrupt Vector, PTD Control Register
13.15.6 SDMA Interrupt Pending RegisterMBAR + 0x1214
Table13-6. SDMA Interrupt Pending Register
13.15.7 SDMA Interrupt Mask RegisterMBAR + 0x1218
Table13-7. SDMA Interrupt Mask Register
13.15.8 SDMA Task Control 0 RegisterMBAR + 0x121C SDMA Task Control 1 RegisterMBAR + 0x121E
SDMA Task Control 1 Register
13.15.9 SDMA Task Control 2 RegisterMBAR + 0x1220 SDMA Task Control 3 RegisterMBAR + 0x1222
Table1 3-9. SDMA Task Control 2 Register SDMA Task Control 3 Register
13.15.10 SDMA Task Control 4 RegisterMBAR + 0x1224 SDMA Task Control 5 RegisterMBAR + 0x1226
13.15.11 SDMA Task Control 6 RegisterMBAR + 0x1228 SDMA Task Control 7 RegisterMBAR + 0x122A
Table13-10. SDMA Task Control 4 Register SDMA Task Control 5 Register
Table13-11. SDMA Task Control 6 Register SDMA Task Control 7 Register
13.15.12 SDMA Task Control 8 RegisterMBAR + 0x122C SDMA Task Control 9 RegisterMBAR + 0x122E
13.15.13 SDMA Task Control A RegisterMBAR + 0x1230 SDMA Task Control B RegisterMBAR + 0x1232
Table13-12. SDMA Task Control 8 Register SDMA Task Control 9 Register
Table1 3-13. SDMA Task Control A Register SDMA Task Control B Register
13.15.14 SDMA Task Control C RegisterMBAR + 0x1234 SDMA Task Control D RegisterMBAR + 0x1236
13.15.15 SDMA Task Control E RegisterMBAR + 0x1238 SDMA Task Control F RegisterMBAR + 0x123C
Table1 3-14. SDMA Task Control C Register SDMA Task Control D Register
Table13-15. SDMA Task Control E Register SDMA Task Control F Register
Page
Page
Page
Page
Page
Page
13.15.24 SDMA Requestor MuxControlMBAR + 0x125C
Table13-24. SDMA Request MuxControl
Page
13.15.25 SDMA task Size0MBAR + 0x1260 SDMA task Size 1MBAR + 0x1264
Table13-25. FIxed REquestors Table
Table13-26. SDMA task Size 0/1
13.15.26 SDMA task 0 & task Size 1 map
13.15.27 SDMA Reserved Register 1MBAR + 0x1268
Table13-27. SDMA task Size Map
Table13-28. SDMA Reserved Register 4
13-24 Freescale Semiconductor
13.15.28 SDMA Reserved Register 2MBAR + 0x126C
13.15.29 SDMA Debug Module Comparator 1, Value1 RegisterMBAR + 0x1270
13.15.30 SDMA Debug Module Comparator 2, Value2 RegisterMBAR + 0x1274
Table13-29. SDMA Reserved Register 2
0:31 res2 Reserved
13.15.31 SDMA
Debug Module Control Register
MBAR + 0x1278
Table13-32. SDMA Debug Module Control Register
Table1 3-33. Comparator 1 Type Bit Encoding
Table1 3-34. Comparator 2 Type Bit Encoding
13.15.32 SDMA Debug Module Status RegisterMBAR + 0x127C
Table13-35. EU Breakpoint encoding
Table13-36. SDMA Debug Module Status Register
13.16 On-Chip SRAM
13.17 Programming Model
Figure 13-1. Task Table
13.17.1 Task Table
Page
13.17.1.1 Integer Mode
13.17.1.2 Pack
13.17.2 Variable Table
Table13-37. Behavior of Task Table Control Bits
Table13-38. Variable Table per Task
Page
Chapter 14 Fast Ethernet Controller (FEC )
14.1 Overview
14.1.1 Features
FEC
14.2 Modes of Operation
14.2.1 Full- and Half-Duplex Operation
14.2.2 10 Mbps and 100Mbps MII Interface Operation
14.2.3 10 Mbps 7-Wire Interface Operation
14.2.4 Address Recognition Options
14.3.1 Detailed Si gnal Descriptions
14.3.1.1 MII Ethernet MAC-PHY Interface
Table14-1. Signal Properties (continued)
14.3.1.2 MII Management Frame Structure
Table14-2. MII: Valid Encoding of TxD, Tx_EN and Tx_ER
Table14-3. MII: Valid Encoding of RxD, Rx_ER and Rx_DV
14.3.1.2.1 MII Management Register Set
14.4 FEC Memory Map and Registers
Table14-4. MMI Format Definitions
Table14- 5. MII Management Register Set
14.4.1 Control and Status (CSR) Memory Map
Table14-6. Module Memory Map
Table 14-7. CSR Counters
14.4.2 MIB Block Counters Memory Map
Table 14-7. CSR Counters
Table1 4-8. MIB Counters
14.5 FEC RegistersMBAR + 0x3000
Table14-8. MIB Counters (continued)
14.5.1 FEC ID RegisterMBAR + 0x3000
Table14-9. FEC ID Register
14.5.2 FEC Interrupt Event RegisterMBAR + 0x3004
Table14-10. FEC Interrupt Event Register
Page
14.5.3 FEC Interrupt Enable RegisterMBAR + 0x3008
14.5.4 FEC Rx Descriptor Active RegisterMBAR + 0x3010
Table1 4-11. FEC Interrupt Enable Register
14.5.5 FEC Tx Descriptor Active RegisterMBAR + 0x3014
Table14-12. FEC Rx Descriptor Active Register
Table14-13. FEC Tx Descriptor Active Register
14.5.6 FEC Ethernet Control RegisterMBAR + 0x3024
Table14-14. FEC Ethernet Control Register
14.5.7 FEC MII Manage ment Frame RegisterMBAR + 0x3040
Table14-15. FEC MII Management Frame Register
14.5.8 FEC MII Speed Control RegisterMBAR + 0x3044
14.5.9 FEC MIB Control RegisterMBAR + 0x3064
Table14-17. Programming Examples for MII_SPEED Register
Table14-18. FEC MIB Control Register
14.5.10 FEC Receive Control RegisterMBAR + 0x3084
Table14-19. FEC Receive Control Register
14.5.11 FEC Hash RegisterMBAR + 0x3088
14.5.12 FEC Tx Control RegisterMBAR + 0x30C4
Table 14-20. FEC Hash Register
Table14-21. FEC Tx Control Register
14.5.13 FEC Physical Address Low RegisterMBAR + 0x30E4
Table14-22. FEC Physical Address Low Register
14.5.14 FEC Physical Address High RegisterMBAR + 0x30E8
14.5.15 FEC Opcode/Pause Duration RegisterMBAR + 0x30EC
Table14-23. FEC Physical Address High Register
Table 14-24. FEC Opcode/Pause Duration Register
14.5.16 FEC Descriptor Individual Address 1 RegisteMBAR + 0x3118
FEC Descriptor Individual Address 2 Register
14.5.17
MBAR + 0x311C
Table1 4-25. FEC Descriptor Individual Address 1 Register
14.5.18 FEC Descriptor Group Address 1 RegisterMBAR + 0x3120
14.5.19 FEC Descriptor Group Address 2 RegisterMBAR + 0x3124
Table14-27. FEC Descriptor Group Address 1 Register
Table14-28. FEC Descriptor Group Address 2 Register
14.5.20 FEC Tx FIFO Watermark RegisterMBAR + 0x3144
Table14-29. FEC Tx FIFO Watermark Register
14.6 FIFO Interface
Table 14-30. FIFO Interface Register Map
14.6.1 FEC Rx FIFO Data RegisterMBAR + 0x3184
14.7 FEC Tx FIFO Data RegisterMBAR + 0x31A4
14.7.1 FEC Rx FIFO Status RegisterMBAR + 0x3188
14.8 FEC Tx FIFO Status RegisterMBAR + 0x31A8
Table14-31. FEC Rx FIFO Status Register FEC Tx FIFO Status Register
Table14-30. FIFO Interface Register Map (continued)
14.8.1 FEC Rx FIFO Cont rol RegisterMBAR + 0x318C FEC Tx FIFO Control RegisterMBAR + 0x31AC
Table14-32. FEC Rx FIFO Control Register FEC Tx FIFO Control Register
Page
Table14-35. FEC Rx FIFO Alarm Pointer Register FEC Tx FIFO Alarm Pointer Register
Table14-36. FEC Rx FIFO Read Pointer Register FEC Tx FIFO Read Pointer Register
14.8.7 FEC Reset Control RegisterMBAR + 0x31C4
Table14-37. FEC Rx FIFO Write Pointer Register FEC Tx FIFO Write Pointer Register
Table14-38. FEC Reset Control Register
Table 1-1.
14.8.8 FEC Transmit FSM RegisterMBAR + 0x31C8
14.9 Initialization Sequence
14.9.1 Hardware Controlled Initialization
Table14-39. FEC Transmit FSM Register
Table14-40. ETHER_EN De-A ssertion Affect on FEC
Table 1-1.
14.9.2 User Initialization (Prior to Asser ting ETHER_EN)
14.9.2.1 Microcontroller Initialization
14.9.3 Frame Control/Status Words
14.9.3.1 Receive Frame Status Word
Table14-41. User Initialization ( Before ETHER_EN)
14.9.3.2 Transmit Frame Control Word
Table14-44. Transmit Frame Control Word Format
14.9.4 Network Interface Options
14.9.5 FEC Frame Reception
14.9.6 Ethernet Address Recognition
Initialization Sequence
Figure 14-2. Ethernet Address Recognition - receive block decisions
Freescale Semiconductor 14-39
Figure 14-3. Ethernet Address Recognition - microcode decisions
Table1 4-45. Destination Address to 6-Bit Hash
14.9.7 Full-Duplex Flow Control
Table14-45. Destination Address to 6-Bit Hash (continued)
14.9.8 Inter-Packet Gap Time
14.9.9 Collision Handling
Table14-46. PAUSE Frame Field Specification
Table14-47. Transmit Pause Frame Registers
14.9.10 Internal and External Loopback
14.9.11 Ethernet Error-Handling Procedure
14.9.11.1 Transmission Errors
14.9.11.2 Reception Errors
Page
Page
Chapter 15 Programmable Serial Controller (PSC)
15.1 Overview
Table15-1. PSC Mode Overview
15.1.1 PSC Functions Over view
Interrupt Control Logic
PSC
Codec
Soft Modem SPI I2S AC97 UART SIR MIR FIR
IrDA
15.1.2 Features
15.2 PSC RegistersMBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Table 15-2. PSC Memory Map
15.2.1 Mode Register 1 (0x00)MR 1
Table15-2. PSC Memory Map (continued)
Table15-3. Mode Register 1 (0x00) for UART Mode
Table15-4. Mode Register 1 (0x00) for SIR Mode
Table15-5. Mode Register 1 (0x00) for other Modes
Table15-6. Parity Mode/ Parity Type Definitions
15.2.2 Mode Register 2 (0x00) MR2
Table15-6. Parity Mode/ Parity Type Definitions
Table15-7. Mode Register 2 (0x00) for UART / SIR Mode
Table15-8. Mode Register 2 (0x00) for other Modes
15.2.3 Status Register (0x04) SR
Table15-9. Stop-Bit Lengths
Table15-10. Status Register (0x04) for UART Mode
Table1 5-11. Status Register (0x04) for SIR Mode
Table15-12. Status Register (0x04) for MIR / FIR Mode
Table15-13. Status Register (0x04) for other Modes
0 = No break received.
Page
Page
15.2.4 Clock Select Register (0x04) CSR
15.2.5 Command Register (0x08)CR
Table15-14. Clock Select Register (0x04) for UART / SIR Mode
Table15-15. Clock Select Register (0x04) for other Modes
Table15-16. Command Register (0x08) for all Modes
Page
PSC RegistersMBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Freescale Semiconductor 15-15
15.2.6 Rx Buffer Register (0x0C) RB
Table15-18. Rx Buffer Register (0x0C) for AC97
Table 15-19. Rx Buffer Register (0x0C) for Codec24
15.2.7 Tx Buffer Register (0x0C)TB
Table15-20. Tx Buffer Register (0x0C) for UART/SIR/MIR/FIR/Codec8/16/32 Modes
Table 15-21. TX Buffer Register (0x0C) for AC97) Modes
15.2.8 Input Port Change Register (0x10) IPCR
Table15-24. Input Port Change Register (0x10) for Codec Mode
Table15-22. Tx Buffer Register (0x0c) for Codec24
Table15-23. Input Port Change Register (0x10) for UART/SIR/MIR/FIR Modes
15.2.9 Auxiliary Control Register (0x10) AC R
Table15-25. PSC 1 Auxiliary Control Register (0x10) for all Modes
15.2.10 Interrupt Status Register (0x14) ISR
Table15-26. Interrupt Status Register (0x14) for UART / SIR Mode
Table15-27. Interrupt Status Register (0x14) other Modes
15.2.11 Interrupt Mask Register (0x14)IMR
Table15-28. Interrupt Mask Register (0x14) for UART / SIR Mode
Table15-29. Interrupt Mask Register (0x14) for other Modes
15.2.12 Counter Timer Upper Register (0x18)CTUR
10:11 12
13
14
15
15.2.13 Counter Timer Lower Register (0x1C)CTLR
15.2.14 Codec Clock Register (0x20)CCR
15-24 Freescale Semiconductor
PSC RegistersMBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Table15-33. Codec Clock Register (0x20)CCR for MIR/FIR Mode
Table15-34. Codec Clock Register (0x20)CCR for other Modes
Table15-32. Codec Clock Register (0x20)CCR for Codec Mode
Mclk = MclkDiv [8:0] + 1
f
15.2.15 AC97 Slots Register (0x24)AC97Slots
Table15-35. AC97 Slots Register (0x24)AC97Slots
Table15-36. AC97 Command Register (0x28)AC97CMD
15.2.16 AC97 Command Register (0x28)AC97CMD
15.2.17 AC97 Status Data Register (0x2C)AC97Data
Table15-37. AC97 Status Data Register (0x2C)AC97Data
15.2.18 Interrupt Vector Register (0x30)IVR
15.2.19 Input Port Register (0x34)IP
Table15-38. Interrupt Vector Register (0x30) for all Modes
Table15-39. Input Port Register (0x34) for UART/SIR/MIR/FIR Modes
Table15-40. Input Port Register (0x34) for Codec Mode
Table15-41. Input Port Register (0x34) for AC97 Mode
15.2.20 Output Port 1 Bit Set (0x38)OP1
15.2.21 Output Port 0 Bit Set (0x3C)OP0
Table1 5-42. Output Port 1 Bit Set Register (0x38) for all Modes
Table15- 43. Output Port 0 Bit Set Register (0x3C) for all Modes
15.2.22 Serial Interface Control Register (0x40)SICR
Table15-44. Serial Interface Control Register (0x40) for all Modes
Page
Page
15.2.23 Infrared Control 1 (0x44)IRCR1
15.2.24 Infrared Control 2 (0x48)IRCR2
15.2.25 Infrared SIR Divide Register (0x4C)IRSDR
Table1 5-47. Infrared Control 2 (0x48) for MIR/FIR Modes
Table15-48. Infrared Control 2 (0x48) for other Modes
For more informations about the SIP pulse see also
15.2.26 Infrared MIR Divide Register (0x50)IRMDR
Table15-49. Infrared SIR Divide Register (0x48) for SIR Mode
Table15-50. Infrared SIR Divide Register (0x48) for other Modes
Table15-51. Infrared MIR Divide Register (0x50) for MIR Mode
Table 15-52. Infrared MIR Divide Register (0x50) for other Modes
15.2.27 Infrared FIR Divide Register (0x54)IRFDR
fbit
Table15-53. Frequency Selection in MIR Mode
Table15-54. Infrared FIR Divide Register (0x54) for MIR Mode
Table15-55. Infrared FIR Divide Register (0x54) for other Modes
Page
15.2.28 Rx FIFO Number of Data (0x58)RFNUM
15.2.29 Tx FIFO Number of Data (0x5C)TFNUM
15.2.30 Rx FIFO Data (0x60)RFDATA
15.2.31 Rx FIFO Status (0x64)RFSTAT
Table15-57. RX FIFO Number of DATA (0x58)
15.2.32 Rx FIFO Control (0x68)RFCNTL
15.2.33 Rx FIFO Alarm (0x6E)RFALARM
Table15-60. Rx FIFO Control (0x68)
0:1 Reserved
Table15-61. Rx FIFO Alarm (0x6E)
15.2.34 Rx FIFO Read Pointer (0x72)RFRPTR
15.2.35 Rx FIFO Write Pointer(0x76)RFWPTR
15.2.36 Rx FIFO Last Read Frame (0x7A)RFLRFPTR
Table 15-62. Rx FIFO Read Pointer (0x72)
Table15-63. Rx FIFO Write Pointer (0x76)
15.2.37 Rx FIFO Last Write Frame PTR (0x7C)RFLWFPTR
15.2.38 Tx FIFO Data (0x80)TFDATA
15.2.39 Tx FIFO Status (0x84)TFSTAT
Table15-65. Rx FIFO Last Write Frame PTR (0x7C)
Table15-66. Tx FIFO STAT (0x84)
15.2.40 Tx FIFO Control (0x88)TFCNTL
15.2.41 Tx FIFO Alarm (0x8E)TFALARM
15.2.42 Tx FIFO Read Pointer (0x92)TFRPTR
Table15-67. Tx FIFO Control (0x88)
Table15-68. Tx FIFO Alarm (0x8E)
15.2.43 Tx FIFO Write Pointer (0x96)TFWPTR
15.2.44 Tx FIFO Last Read Frame (0x9A)TFLRFPTR
15.2.45 Tx FIFO Last Write Frame PTR (0x9C)TFLWFPTR
Table15-70. Tx FIFO Write Pointer (0x96)
Table1 5-71. Tx FIFO Last Read Frame PTR (0x9A)
15.3 PSC Operation Modes
15.3.1 PSC in UART Mode
15.3.1.1 Block Diagram and Signal Definition for UART Mode
Table15-73. PSC Modes Overview
f
Figure 1-1PSC UART Block Diagram
15.3.1.2 UART Clock Generation
15.3.1.3 Transmitting in UART Mode
Baud rate = IPB Clock 32 x divider {CTUR:CTLR} Divider = 66 MHz 32 x 9600 = 215(decimal ) = 0x00D7
RxD
PSC
16-Bit Divider
TxD
15.3.1.4 Receiving in UART Mode
Figure 15-5. Timing DiagramReceiver
15.3.1.5 Configuration Sequence for UART Mode
15.3.2 PSC in Codec Mode
Table15-76. General Configuration Sequence for UART mode
Table15-77. Signal Definition for all Codec Modes
15.3.2.1 Block Diagram and Signal Definition for Codec Mode
CDM PSC
15.3.2.2 Codec Clock and FrameSync Generation
Mclk divider BitClk divider Frame divider
Figure 15-8. Clock Generation Diagram for Codec Mode
Table15-78. PSC Signal Description for Codec Mode
PSCCDM
Mclk = MclkDiv [8:0] +1
15.3.2.3 Transmitting and Receiving in Soft Modem Codec Mode
f BitClk = CCR[8:15] +1
Frame sync width = CTUR[0:7] + 1
Frame = CCR[0:7] +1
In the Codec Soft Modem mode the PSC send only one data word per frame.
15.3.2.4 Transmitting and Receiving in ESAI Mode (Enhanced Serial Audio Interface)
Table15-80. 32-Bit Soft ModemMaster Mode
Figure 15-10. ESAI Data Transmission
Table15-81. 16-bit ESAI Master Mode for PSC1
Frame CLK DATA
15.3.2.5 Transmitting and Receiving in Cell Phone Mode
Figure 15-11. Clock distribution network in cell phone mode
PSC 1
PSC 2,3 or 6
Clock multiply by 2 Mclk (not used)
Clock Gener- ation
15.3.2.6 Transmitting and Receiving in I2S Master Mode
Table15-82. 24-Bit Cell Phone Master Mode for PSC1
Table15-83. 24-Bit Cell Phone Slave Mode for PSC2
Figure 15-12. I2S-Data Transmission
Table15- 84. 32-bit I2S Master Mode for PSC1
LRCK (Frame) SCLK (CLK) SDATA
15.3.2.7 Transmitting and Receiving in SPI Mode
DSCKL delay =
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
CCR[0:7] +1 DTL = IPB clock frequency
CT[0:15] +2
+ 3 Mclk frequency
SCK SS MOSI MISO
15.3.3 PSC in AC97 Mode
Table15-86. 8-bit SPI Slave mode for PSC2
15.3.3.1 Block Diagram and Signal Definition for AC97 Mode
PSC
Logic
SDATA_OUT
15.3.3.2 Generate a reset pulse for the external AC97 Codec device
15.3.3.3 AC97 Low-Power Mode
15.3.3.4 Transmitting and Receiving in Normal AC97 Mode
15.3.3.5 Transmitting and Receiving in Enhanced AC97 Mode
Table15-88. General Configuration Example for normal AC97 Mode
Table15-89. General Configuration Example for enhanced AC97 Mode
15.3.4 PSC in IrDA mode
15.3.4.1 PSC in SIR Mode
15.3.4.1.1 Block Diagram and Signal Definition for SIR Mode
15.3.4.1.2 Transmitting and Receiving in SIR Mode
15.3.4.1.3 Configuration Sequence Example for SIR Mode
15.3.4.2 PSC in MIR Mode
15.3.4.2.1 Block Diagram and Signal Definition for MIR Mode
Table15-91. Configuration Sequence Example for SIR Mode
15.3.4.2.2 Transmitting and Receiving in MIR Mode
CDM
This zero was insert after five consecutive ones!
15.3.4.2.3 Serial Interaction Pulse (SIP)
Figure 15-20. Serial Interaction Pulse (SIP)
15.3.4.2.4 Configuration Sequence Example for MIR Mode
Table15-92. Configuration Sequence Example for MIR Mode
15.3.4.3 PSC in FIR Mode
15.3.4.3.1 Block Diagram and Signal Definition for FIR Mode
15.3.4.3.2 Transmitting and Receiving in FIR Mode
Figure 15-21. Data Format in FIR Mode
Table15-92. Configuration Sequence Example for MIR Mode
15.3.4.3.3 Configuration Sequence Example for FIR Mode
15.4 PSC FIFO System
Table 15-93. Configuration Sequence Example for FIR Mode
Page
Page
15.4.2 TX FIFO
15.4.3 Looping Modes
Rx
Tx
15.4.3.1 Automatic Echo Mode
15.4.4 Multidrop Mode
Figure 15-26. Timing DiagramMultidrop Mode
Chapter 16 XLB Arbiter
16.1 Overview
16.1.1.2 Bus Grant Mechanism
16.1.1.2.1 Bus Grant
16.1.1.2.2 Parking Modes
16.1.1.3 Configuration, Status, and Interrupt Generation
16.1.1.4 Watchdog Functions
16.1.1.4.1 Timer Functions
16.2 XLB Arbiter RegistersMBAR + 0x1F00
16.2.1 Arbiter Configuration Register (R/W)MBAR + 0x1F40
Table16-1. Arbiter Configuration Register
16.2.2 Arbiter Version Register (R)MBAR + 0x1F44
16.2.3 Arbiter Status Re gister (R/W)MBAR + 0x1F48
Table16-2. Arbiter Version Register
16.2.4 Arbiter Interrupt Enable Register (R/W)MBAR + 0x1F4C
Table1 6-3. Arbiter Status Register
16.2.5 Arbiter Address Capture Register (R)MBAR + 0x1F50
Table16-4. Arbiter Interrupt Enable Register
Table16-5. Arbiter Address Capture Register
16.2.6 Arbiter Bus Signal Capture Register (R)MBAR + 0x1F54
16.2.7 Arbiter Address Tenure Time-Out Register (R/W)MBAR + 0x1F58
Table16-6. Arbiter Bus Signal Capture Register
Table16-7. Arbiter Address Tenure Time-Out Register
16.2.8 Arbiter Data Tenure Time-Out Register (R/W)MBAR + 0x1F5C
16.2.9 Arbiter Bus Activity Time-Out Register (R/W)MBAR + 0x1F60
Table16-8. Arbiter Data Tenure Time-Out Register
Table16-9. Arbiter Bus Activity Time-Out Register
16.2.10 Arbiter Master Priority Enable Register (R/W)MBAR + 0x1F64
Table16-10. Arbiter Master Priority Enable Register
Table16-11 . Hardware Assignments of Master Priority
16.2.11 Arbiter Master Priority Register (R/W)MBAR + 0x1F68
Table1 6-12. Arbiter Master Priority Register
Table16-11 . Hardware Assignments of Master Priority
16.2.12
Arbiter Snoop Window Register
(RW)MBAR + 0x1F70
Table16-13. Arbiter Snoop Window Register
16.2.13
MBAR + 0x1F00-1F3C, 0x1F74-1FFF
Registers
Arbiter Reserved
Page
Chapter 17 Serial Peripheral Interface (SPI )
17.1 Overview
IP bus
Figure 17-1. Block DiagramSPI
17.1.1 Features
17.2 SPI Signal Description
17.2.1 Master In /Slave Out (MISO )
17.2.2 Master Out /Slave In (MOSI )
17.2.3 Serial Clock ( SCK)
17.2.4 Slave-Select ( SS)
17.3 SPI RegistersMBAR + 0x0F00
17.3.1 SPI Control Register 1MBAR + 0x0F00
Table17-2. SPI Control Register 1
17.3.2 SPI Control Register 2MBAR + 0x0F01
Table1 7-3. SS Input/Output Selection
Table17-4. SPI Control Register 2
17.3.3 SPI Baud Rate RegisterMBAR + 0x0F04
17.3.4 SPI Status Re gister MBAR + 0x0F05
Table17-7. SPI Baud Rate Selection
Table17-8. SPI Status Register
17.3.5 SPI Data RegisterMBAR + 0x0F09
17.3.6 SPI Port Data RegisterMBAR + 0x0F0D
17.3.7 SPI Data Directio n RegisterMBAR + 0x0F10
Table 17-9. SPI Data Register
Table17-10. SPI Port Data Register
17.4 Functional Description
17.4.1 General
17.4.2 Master Mode
17.4.3 Slave Mode
17.4.4 Transmission Formats
Figure 17-2. Master/Slave Transfer Block Diagram
17.4.4.1 Clock Phase and Polarity Controls
17.4.4.2 CPHA = 0 Transfer Format
Figure 17-3. SPI Clock Format 0 (CPHA = 0)
17.4.4.3 CPHA = 1 Transfer Format
Figure 17-4. SPI Clock Format 1 (CPHA = 1)
17.4.5 SPI Baud Rate Generation
Figure 17-5. Baud Rate Divisor Equation
BaudRateDivisor SPPR 1+()2SPR 1+()
17.4.6 Special Features
17.4.6.1 SS Output
17.4.6.2 Bidirectional Mode (MOMI or SISO)
Table17-12. Normal Mode and Bidirectional Mode
=
17.4.7 Error Conditions
17.4.7.1 Write Collision Error
17.4.7.2 Mode Fault Error
17.4.8 Low Power Mode Options
17.4.8.1 SPI in Run Mode
17.4.9 SPI Interrupts
17.4.9.1 MODF Description
17.4.9.2 SPIF Description
Page
Chapter 18 Inter-Integrated Circuit (I2C)
18.1 Overview
18.1.1 Features
Figure 18-1. Block DiagramI2C Module
18.2 I2C Controller
18.2.1 START Signal
18.2.2 STOP Signal
Table18-1. I2C Terminology
18.2.2.1 Slave Address Transmission
Figure 18-2. Timing DiagramStart, Address Transfer and Stop Signal
18.2.2.2 Data Transfer
Figure 18-3. Timing DiagramData Transfer
18.2.2.3 Acknowledge
18.2.2.4 Repeated Start
Figure 18-5. Data Transfer, Combined Format
18.2.2.5 Clock Synchronization and Arbitration
18.3 I2C Interface Registers
18.3.1 I2C Address Register (MADR)MBAR + 0x3D00 / 0x3D40
18.3.2 I2C Frequency Divider Register (MFDR)MBAR + 0x3D04 / 0x3D44
Table 18-2. I2C Address Register
Table18-3. I2C Frequency Divider Register
Table18-4. I2C Frequency Divider Bit Selection
Page
Page
Page
Page
18.3.3 I2C Control Register (MCR)MBAR + 0x3D08 / 0x3D48
Tabl e 18- 5. I 2C Control Register
Page
18.3.4 I2C Status Register (MSR)MBAR + 0x3D0C / 0x3D4C
18.3.5 I2C Data I/O Register (MDR)MBAR+ x3D10 / 0x3D50
Table18-7. I2C Data I /O Register
18.3.6 I2C Interrupt Control RegisterMBAR + 0x3D20
Table18-8. I2C Interrupt Control Register
18.3.7 I2C Filter Register (MIFR)MBAR + 0x3D24
Table18-9. I2C Filter Register
18.4 Initialization Sequence
18.5 Transfer Initiation and Interrupt
18.5.1 Post-Transfer Software Response
18.5.2 Slave Mode
18.5.3 Special Note on AKF
Transfer Initiation and Interrupt
Freescale Semiconductor 18-21
Figure 18-9. Software Flowchart of Typical I2C Interrupt Routine
Page
Chapter 19 Controller Area Network ( MSCAN )
19.1 Overview
MUX Presc.
Figure 19-1. MSCAN Block Diagram
MSCAN
19.2 Features
19.3 External Signals
19.3.1 RXCAN CAN Re ceiver Input Pin
19.3.2 TXCAN CAN Transmitter Output Pin
19.4 CAN System
19.5 Memory Map / Register Definition
19.5.1 Module Memor y Map
Table19-1. MSCAN Register Organization
Table19-2. Module Memory Map
Table19-1. MSCAN Register Organization (continued)
19.5.2 Register Descriptions
Table19-2. Module Memory Map (continued)
19.5.3 MSCAN Control Register 0 (CANCTL0)MBAR + 0x0900 / 0x980
Table19-3. MSCAN Control Register 0
Page
19.5.4 MSCAN Control Register 1 (CANCTL1)MBAR + 0x0901 / 0x981
Table19-4. MSCAN Control Register 1
19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)MBAR + 0x0904 / 0x984
6SLPAK
7INITAK
Table19-5. MSCAN Bus Timing Register 0
Table1 9-6. Baud Rate Prescaler
19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)MBAR + 0x0905 / 0x985
Table19-7. MSCAN Bus Timing Register 1
Table19-8. Time Segment 1 Values
Table19-6. Baud Rate Prescaler (continued)
Bit Time = (Prescaler value) (Number of Time Quanta) fCANCLK
19.5.7 MSCAN Receiver Flag Register (CANRFLG)MBAR+0x0908 / 0x988
Table19-9. Time Segment 2 Values
Table19-10. MSCAN Rece iver Flag Register
Table1 9-8. Time Segment 1 Values (continued)
Page
19.5.8 MSCAN Receiver Interr upt Enable Register (CANRIER)MBAR + 0x0909 / 0x989
Table19-11. MSCAN Receiver Interrupt Enable Register
19.5.9 MSCAN Transmitter Flag Register (CANTFLG)MBAR + 0x090C / 0x98C
Table 19-12. MSCAN Transmitter Flag Register
19.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)MBAR+0x090D / 0x098D
19.5.11 MSCAN Transmitter Message Abort Request (CANTARQ)MBAR + 0x0910 / 0x0990
Table19-13. MSCAN Transmitter Interrupt Enable Register
Table19-14. MSCAN Transmitter Message Abort Request Register
19.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)MBAR +0x0911 / 0x0991
19.5.13 MSCAN Transmit Buffer Selection (CANTBSEL)MBAR + 0x0914 /0x0991
Table19-15. MSCAN Transmitter Message Abort Acknowledgement Register
Table1 9-16. MSCAN Transmit Buffer Selection Register
19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)MBAR + 0x0915 / 0x0995
Table19-17. MSCAN ID Acceptance Control Register
Table19-18. Identifier Acceptance Hit Indication
Table1 9-19. Identifier Acceptance Mode Settings
19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C
19.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D
Table19-20. MSCAN Receive Error Counter Register
Table19-21. MSCAN Transmit Error Counter Register
Page
Table19-23. MSCAN ID Acceptance Registers (4 - 7)
Adress Offset 0x930 / 0x9B0 CANIDR4
Adress Offset 0x931 / 0x9B1 CANIDR5
Adress Offset 0x934 / 0x9B4 CANIDR6
Adress Offset 0x935 / 0x9B5 CANIDR7
Page
Table19-25. MSCAN ID MaskRegisters (4 - 7)
Adress Offset 0x938 / 0x9B8 CANIDMR4
Adress Offset 0x939 / 0x9B9 CANIDMR5
Adress Offset 0x93C / 0x9BC CANIDMR6
Adress Offset 0x93D / 0x9BD CANIDMR7
19.6 Programmers Model of Message Storage
Table19-26. Message Buffer Organization
Table19-27. Receive / Transmit Message Buffer Extended Identifier
Table19-27. Receive / Transmit Message Buffer Extended Identifier (continued)
19.6.1 Identifier Registers (IDR0-3)
19.6.2 Data Segment Registers (DSR0-7)
Table 19-28. Standard Identifier Mapping
19.6.3 Data Length Register (DLR)
19.6.4 MSCAN Transmit Buffer Priority Register (TBPR)MBAR + 0x0979 / 0x09F9
Table19-29. Data Length Codes
Table19-30. MSCAN Transmit Buffer Priority Register
19.6.5 MSCAN Time Stam p Register High (TSRH)MBAR + 0x097C / 0x09FC
19.7 Functional Description
19.7.1 General
Table19-31. MSCAN Time Stam p Register (High Byte)
Table19-32. MSCAN Time Stamp Register (Low Byte)
19.7.2 Message Storage
Receiver
Transmitter
RxBG
TxBG
Tx1
19.7.2.2 Transmit Structures
19.7.2.3 Receive Structures
19.7.3 Identifier Acceptance Filter
19-30 Freescale Semiconductor
Figure 19-4. 32-bit Maskable Identifier Acceptance Filter
Figure 19-5. 16-bit Maskable Identifier Acceptance Filters
Freescale Semiconductor 19-31
Figure 19-6. 8-bit Maskable Identifier Acceptance Filters
19.7.4 Protocol Violation Protection
19.7.5 Clock System
Figure 19-7. MSCAN Clocking Scheme
-------------------------------------------------------=
f
MSCAN
f Prescaler value()
Figure 19-8. Segments within the Bit Time
Table19-33. Time Segment Syntax
Table19-34. CAN Standard Compliant Bit Time Segment Settings
Bit Rate f number of Time Quanta ()
-----------------------------------------------------------------------------------------=
19.7.6 Timer Link
19.7.7 Modes of Operation
19.7.7.1 Normal Modes
19.7.7.2 Listen-Only Mode
19.7.8 Low Power Options
19.7.8.1 CPU Run Mode
19.7.8.2 CPU Sleep Mode
19.7.8.3 CPU Deep Sleep Mode
19.7.8.4 MSCAN Sleep Mode
Figure 19-9. Sleep Request / Acknowledge Cycle
19.7.8.5 MSCAN Initialization Mode
Wait Idle Tx/Rx Message Active
Sleep
StartUp for Idle
Figure 19-11. Initialization Request/Acknowledge Cycle
19.7.9 Description of Interrupt Operation
Page
19.7.9.4 Error Interrupt
19.7.10 Interrupt Acknowledge
19.7.11 Recovery from STOP or WAIT
Page
Chapter 20 Byte Data Link Controller (BDLC)
20.1 Overview
20.2 Features
20.3 Modes of Operation
Figure 20-1. BDLC Operating Modes State Diagram
Power Off
Reset
Disabled
BDLC Wait
Run
Page
20.4 Block Diagram
CPU INTERFACE
To Physical Interface
To CPU
CPU Interface
Protocol Handler
MUX Interface
20.5 Signal Description 20.6 Overview
20.6.1 Detailed Si gnal Descriptions
20.6.1.1 TXB - BDLC Transmit Pin
20.6.1.2 RXB - BDLC Receive Pin
20.7 Memory Map and Registers
Table20-2. BDLC Control Register 1
20.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x1300
Table 20-3. BDLC State Vector Register
Table 1-1. Interrupt Summary
20.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x1304
Table20-4. BDLC Control Register 2
Table 1-2. Transmit In-Frame Response Control Bit Priority Encoding
Figure 20-3. Types of In-Frame Response
Type 0 - No IFR
Type 3 - Multiple Bytes From a Single Responder (with or without CRC)
Type 1 - Single Byte From a Single Responder (without CRC)
Type 2 - Single Byte From Multiple Responders (without CRC)
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20.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x1305
20.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x1308
Table20-5. BDLC Data Register
Table20-6. BDLC Analog Round Trip Delay Register
Table20-7. BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment
20.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309
Table20-8. BDLC Rate Select Register
Table20-7. BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment (continued)
20.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C
20.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D
Table20-9. BDLC Rate Selection for Binary Frequencies [CLKS = 1]
Table20-10. BDLC Rate Selection for Integer Frequencies [CLKS = 0]
Table20-11. BDLC Control Register
20.8 Functional Description
20.8.1.2 J1850 VPW Symbols
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20.8.1.3 J1850 VPW Valid/Invalid Bits & Symbols
Table20-13. BDLC Transmitter VPW Symbol Timing for Integer Frequencies
Table20-14. BDLC Transmitter VPW Symbol Timing for Binary Frequencies
Table20-15. BDLC Receiver VPW Symbol Timing for Integer Frequencies
1
Table20-13. BDLC Transmitter VPW Symbol Timing for Integer Frequencies (continued)
Table20-16. BDLC Receiver VPW Symbol Timing for Binary Frequencies
Table20-17. BDLC Receiver VPW 4X Symbol Timing for Integer Frequencies
Table20-18. BDLC Receiver VPW 4X Symbol Timing for Binary Frequencies
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Figure 20-10. J1850 VPW Bitwise Arbitrations
Transmitter A Transmitter B J1850 Bus
20.8.1.4 J1850 Bus Errors
20.8.2 Mux Interface
20.8.2.1 Mux Interface - Rx Digital Filter
Table20-19. BDLC module J1850 Error Summary
20.8.3 Protocol Handler
4-Bit Up/Down Counter up/down out dq
Input Sync dq
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20.8.4 Transmitting A Message
20.8.4.1 BDLC Transmission Control Bits
20.8.4.2 Transmitting Exceptions
20.8.4.3 Aborting a Transmission
Freescale Semiconductor 20-33
Figure 20-13. Basic BDLC Transmit Flowchart
BB
20.8.5 Receiving A Message
20.8.5.1 BDLC Reception Control Bits
20.8.5.2 Receiving a Message with the BDLC module
20.8.5.3 Filtering Received Messages
20.8.5.4 Receiving Exceptions
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20-36 Freescale Semiconductor
Figure 20-14. Basic BDLC Receive Flowchart
20.8.6 Transmitting An In-Frame Response (IFR)
20.8.6.1 IFR Types Supported by the BDLC module
20.8.6.2 BDLC IFR Transmit Control Bits
20.8.6.3 Transmit Single Byte IFR
20.8.6.4 Transmit Multi-Byte IFR 1
20.8.6.5 Transmit Multi-Byte IFR 0
20.8.6.6 Transmitting An IFR with the BDLC module
Table20-20. IFR Control Bit Priority Encoding
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Figure 20-15. Transmitting A Type 1 IFR
Figure 20-16. Transmitting A Type 2 IFR
20.8.6.7 Transmitting IFR Exceptions
Freescale Semiconductor 20-43
Figure 20-17. Transmitting A Type 3 IFR
20.8.7 Receiving An In-Frame Response (IFR)
20.8.7.1 Receiving an IFR with the BDLC module
Figure 20-18. Receiving An IFR With the BDLC module
20.8.7.2 Receiving IFR Exceptions
20.8.8 Special BDLC Module Operations
20.8.8.1 Transmitting Or Receiving A Block Mode Message
20.8.8.2 Transmitting Or Receiving A Message In 4X Mode
Freescale Semiconductor 20-47
Figure 20-19. Basic BDLC Module Transmit Flowchart
BB
20.8.9 BDLC Module Initialization
20.8.9.1 Initialization Sequence
20.8.9.2 Initializing the Configuration Bits
20.8.9.3 Exiting Loopback Mode and Enabling the BDLC module
20.8.9.4 Enabling BDLC Interrupts
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20-50 Freescale Semiconductor
Resets
20.9 Resets
Figure 20-20. Basic BDLC Module Initialization Flowchart
20.9.1 General
Chapter 21 Debug Support and JTAG Interface
21.1 Overview
21.2 TAP Link Module (TLM) and Slave TAP Implementation
TAP
(TLM )
TAP
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21.3 TLM and TAP Signal Descriptions
21.3.1 Test Reset ( TRST)
21.3.2 Test Clock ( TCK)
21.3.3 Test Mode Select ( TMS)
21.3.4 Test Data In ( TDI)
21.4 Slave Test Reset (STRST)
21.4.1 Enable SlaveENA [0: n]
21.4.2 Select DR LinkSEL [0: n]
21.4.3 Slave Test Data OutSTDO [0:n ]
21.5 TAP State Machines
21.6 e300 Core JTAG /COP Serial Interface
21.7 TLM Link DR Instructions
Long Shift Register Latch
21.8 TLM Test Instructions
21.8.4 EXTEST
21.8.5 CLAMP
21.8.6 HIGHZ
21.9 e300 COP/BDM Interface
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Appendix A Acronyms and Terms
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
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T
U
V
W
X
Appendix B List of Registers
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