MPC5200B Users Guide, Rev. 1
20-26 Freescale Semiconductor
Functional Description
20.8.1.4 J1850 Bus Errors
The BDLC module detects several types of transmit and receive errors which can occur during the transmission of a message onto the J1850
bus.
• Transmission Error
If the BDLC module is transmitting a message and the message received contains a symbol error, a framing error, a bus fault, a
BREAK symbol, or a logic ‘1’ symbol when a logic “0” is being transmitted, this constitutes a transmission error. Receiving a logic
‘0’ symbol when transmitting a logic ‘1’ is considered a loss of arbitration condition (See Message Arbitration) and not a
transmission error. When a transmission error is detected, the BDLC module will immediately cease transmitting. Further
transmission or reception will be disabled until a valid EOF symbol is detected on the J1850 bus. The error condition is reflected
by setting the symbol invalid or out of range flag in the BDLC State Vector Register register. If the interrupt enable bit (IE in BDLC
Control Register 1) is set, an interrupt request from the BDLC module is generated. Reading the BDLC State Vector Register register
will clear this flag.
• CRC Error
A cyclical redundancy check (CRC) error is detected when the data bytes and CRC byte of a received message are processed, and
the CRC calculation result is not equal to $C4.The CRC code should detect any single and 2 bit errors, as well as all 8 bit burst
errors, and almost all other types of errors. The CRC error flag (in BDLC State Vector Register) is set when a CRC error is detected.
If the interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt request from the BDLC module is generated. Reading
the BDLC State Vector Register register will clear this flag.
• Symbol Error
A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the J1850 bus. See
sections Invalid Passive Bit and Invalid Active Bit which define invalid symbols.The symbol invalid or out of range flag (in BDLC
State Vector Register) is set when a symbol error is detected. If the interrupt enable bit (IE in BDLC Control Register 1) is set, an
interrupt request from the BDLC module is generated. Reading the BDLC State Vector Register register will clear this flag.
• Framing Error
A framing error is detected when a received symbol occurs in an inappropriate location in the message frame. The following
situations result in framing errors:
— An active logic “0” or logic “1” received as the first symbol of the frame.
— An SOF symbol received in any location other than the first symbol of a frame. Erroneous locations include: Within the data
portion of a message or IFR; Immediately following the EOD in a message or IFR.
— An EOD symbol received on a non-byte boundary in a message or IFR.
— An active logic “0” or logic “1” received immediately following the EOD at the end of an IFR.
The symbol invalid or out of range flag (in BDLC State Vector Register) is set when a framing error is detected. If the interrupt
enable bit (IE in BDLC Control Register 1) is set, an interrupt request from the BDLC module is generated. Reading the BDLC
State Vector Register register will clear this flag.
• Bus Fault
If a bus fault occurs, the response of the BDLC module will depend upon the type of bus fault.
If the bus is shorted to VDD, the BDLC module will wait for the bus to fall to a passive state before it will attempt to transmit a
message. As long as the short remains, the BDLC will never attempt to transmit a message onto the J1850 bus.
If the bus is shorted to ground, the BDLC module will see an idle bus, begin to transmit the message, and then detect a transmission
error, since the short to ground would not allow the bus to be driven to the active (dominant) state. The BDLC module will wait for
assertion of the receive pin for (64 - analog round trip delay) tbdlc cycles, after assertion of the transmit pin, before detecting the
error. If the transmission is an IFR, the BDLC module will wait for (280 - analog round trip delay) tbdlc cycles before detecting an
error. The “analog round trip delay” is determined by the value stored in the BDLC Analog Round Trip Delay Register register. The
BDLC module will set the symbol invalid or out of range flag (in BDLC State Vector Register), abort that transmission and wait for
the next CPU command to transmit. In this case, the transmitter does not have to wait for an EOF symbol to be received to be
enabled. If the interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt request from the BDLC module is generated.
Reading the BDLC State Vector Register register will clear this flag.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC module will resume normal operation. If the bus
fault is permanent, it may result in permanent loss of communication on the J1850 bus.
• BREAK - Break
Any BDLC transmitting at the time a BREAK is detected will treat the BREAK as if a transmission error had occurred, and halt
transmission.
If while receiving a message the BDLC module detects a BREAK symbol, it will treat the BREAK as a reception error.