Freescale Semiconductor MPC5200B Chapter 4 Resets and Reset Configuration

Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 4-1
Chapter 4
Resets and Reset Configuration
4.1 Overview
The following sections are contained in this document:
•Hard and Soft Reset Pins
•Reset Sequence
•Reset Operation
•Other Resets
•Reset Configuration
4.2 Hard and Soft Reset Pins
MPC5200B has three primary reset pins, which are implemented as open drain I/Os1:
• Power-On Reset—PORRESET
• Hard Reset—HRESET
• Soft Reset—SRESET
PORRESET is a power-on reset input. It is asserted by an external source and must be held active for a specified period of time until power
is stable to the MPC5200B.
HRESET and SRESET can be asserted by an external source or they can be asserted by reset generation logic internal to MPC5200B.
Internal reset logic analyzes all internal and external reset sources and asserts internal and external reset signals appropriately.
When a hard reset (HRESET) is detected, reset logic counters hold internal and external HRESET for a minimum of 4096 reference clock
cycles or until the external HRESET source is released, whichever is longer.
4.2.1 Power-On Reset—PORRESET
PORRESET must be asserted externally when power is applied to the system for a required period of time (see Section 4.4, Reset Operation).
When PORRESET is asserted, internal logic forces HRESET and SRESET active. PORRESET must remain asserted until the MPC5200B
system oscillator begins oscillation and the system APLL establishes a locked condition.
During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of various vital internal MPC5200B
functions. The reset configuration word is latched internally when HRESET is released.
When initiated by PORRESET, HRESET asserts and remains asserted for 4096 reference clocks after PORRESET is released.
Source of power-on reset is an external, board level reset source like a push button, reset control logic, etc.
4.2.2 Hard Reset—HRESET
HRESET is a bidirectional signal with a Schmitt-trigger input and an open drain output. HRESET requires an external pull-up. Assertion of
external HRESET causes external HRESET and SRESET, and internal hard and soft resets, to be asserted for at least 4096 reference clock
cycles.
During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of various vital internal MPC5200B
functions. The reset configuration word is latched internally when PORRESET or HRESET is released.
HRESET can also be asserted by internal sources. When HRESET is asserted internally, external HRESET and SRESET are also asserted.
Sources of hard reset are:
• PORRESET or HRESET pins asserted
• Hard reset asserted by debug module
• Reset signal asserted by watchdog timer or checkstop reset
1. All “open drain” outputs of MPC5200B are actually regular 3-state output drivers with the output data tied low, and the output enable controlled. Thus,
unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power rail if the external signal is driven above the
MPC5200B I/O power rail voltage.