Freescale Semiconductor MPC5200B - page 31

List of Tables
Tabl e Page
Number Number
MPC5200B Users Guide, Rev. 1
LOT-8 Freescale Semiconductor
15-63 Tx FIFO Control (0x88) ........................................................................................................................................15-37
15-64 Tx FIFO Alarm (0x8E) ..........................................................................................................................................15-37
15-65 Tx FIFO Read Pointer (0x92) ............................................................................................................... ................15-37
15-66 Tx FIFO Write Pointer (0x96) ...............................................................................................................................15-38
15-67 Tx FIFO Last Read Frame PTR (0x9A) .................................................................................. ..............................15-38
15-68 Tx FIFO Last Write Frame PTR(0x9C) ................................................................................................................15-38
15-69 PSC Modes Overview ...................................... ......................................................................................... ............15-39
15-70 Clock Short Cuts ................. ........................................................................................ ..........................................15-39
15-71 PSC Signal Description for UART Mode ............................................ .................................................................15-40
15-72 General Configuration Sequence for UART mode ....................... ........................................................................15-43
15-73 Signal Definition for all Codec Modes .................................................................................... ..............................15-44
15-74 PSC Signal Description for Codec Mode ....................................................................... .......................................15-46
15-75 16-Bit “soft Modem“ Slave Mode ............................................................................................. ............................15-50
15-76 32-Bit “soft Modem“ Master Mode ........................ .................................................................................... ..........15-51
15-77 24-Bit Cell Phone Master Mode for PSC1 ............................................... .............................................................15-52
15-78 24-Bit Cell Phone Slave Mode for PSC2 ............................. .................................................................................15-52
15-79 8-bit SPI Slave mode for PSC2 ................................... ....................................................................................... ...15-53
15-80 32-bit SPI Master mode for PSC3 ........................................................ .................................................................15-53
15-81 32-bit I2S Master Mode for PSC1 .............................................................................. ...........................................15-54
15-82 PSC Signal Description for AC97Mode .......... ....................................................................................... ..............15-56
15-83 General Configuration Sequence for AC97 Mode ........................................ ........................................................15-58
15-84 Signal Description for IrDa Mode ....................................................................... ..................................................15-58
15-85 Configuration Sequence Example for SIR Mode ..................................................... .............................................15-60
15-86 Configuration Sequence Example for MIR Mode .................................................................................. ..............15-62
15-87 Configuration Sequence Example for FIR Mode ..................................................... .............................................15-64
16-1 Arbiter Configuration Register .............................................................................. ..................................................16-4
16-2 Arbiter Version Register ......... ....................................................................................... .........................................16-5
16-3 Arbiter Status Register ..................... ....................................................................................... ................................16-5
16-4 Arbiter Interrupt Enable Register .................................................. ..........................................................................16-6
16-5 Arbiter Address Capture Register ........................ ....................................................................................... ............16-7
16-6 Arbiter Bus Signal Capture Register ...................................................... .................................................................16-8
16-7 Arbiter Address Tenure Time-Out Register ........................................................ ....................................................16-8
16-8 Arbiter Data Tenure Time-Out Register ........ ....................................................................................... ..................16-9
16-9 Arbiter Bus Activity Time-Out Register .............................................. ...................................................................16-9
16-10 Arbiter Master Priority Enable Register ......................................................................... .......................................16-10
16-11 Hardware Assignments of Master Priority ........................................... .................................................................16-10
16-12 Arbiter Master Priority Register ............................................................... .............................................................16-11
16-13 Arbiter Snoop Window Register ...........................................................................................................................16-12
16-14 Arbiter Reserved Registers .................................................................................. ..................................................16-13
17-1 SPI External Signal Descriptions ................................ ......................................................................................... ...17-2
17-2 SPI Control Register 1 ......................................................................................... ....................................................17-3
17-3 SS Input/Output Selection ....................................................... ...............................................................................17-4
17-4 SPI Control Register 2 ......................................................................................... ....................................................17-4
17-5 Bidirectional Pin Configurations ..................................................................... ........................................................17-5
17-6 SPI Baud Rate Register ...................................... ....................................................................................... ..............17-5
17-7 SPI Baud Rate Selection ...................................................................................... ....................................................17-6
17-8 SPI Status Register ............................................. ....................................................................................... ..............17-6
17-9 SPI Data Register ........................... ....................................................................................... ..................................17-7
17-10 SPI Port Data Register ................................................................................... ..........................................................17-7
17-11 SPI Data Direction Register ......................... .................................................................................... .......................17-7
18-1 I2C Terminology ....................................................................... ...............................................................................18-2
18-2 I2C Address Register ............................. .................................................................................... ..............................18-5
18-3 I2C Frequency Divider Register .............................. ......................................................................................... .......18-6
18-4 I2C Tap and Prescale Values ..................... ..................................................................................... .........................18-6