Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-9
The SS pin is normally an input which should remain in the inactive high state. However, in the master mode, if the associated data direction
bit (SPIDDR bit 4) is set, then the SS pin is a general-purpose output or the slave select output depending on the state of the SSOE bit.
General-purpose output (SSOE = 0) or slave select output (SSOE = 1) is specified by the SSOE bit in SPI control register 1. When this pin is
being used as the output pin with SPIDDR bit 4 set, the mode error function for the master is disabled (MODF in the SPI status register).
The SS output becomes low during each transmission and is high when the SPI is in the idling state. If the SS input becomes low while the
SPI is configured as a master, it indicates a mode fault error where more than one master may be trying to drive the MOSI and SCK lines
simultaneously. In this case, the SPI immediately clears the data direction bits associated with the MISO, MOSI (or MOMI), and SCK pins
so that these pins become inputs. This mode fault error also clears the SPE and MSTR control bits and sets the mode fault (MODF) flag in
the SPI status register. If the SPI interrupt enable bit (SPIE) is set when the MODF bit gets set, then an SPI interrupt sequence is also requested
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master.
The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control
register 1 (17.4.4 Transmission Formats).
17.4.3 Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. In slave mode, SCK is the SPI clock input from the
master, and SS is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low
until the transmission is complete.
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit in SPI control
register 2 and the MSTR control bit. While in slave mode, the SS input controls the serial data output pin; if SS is high (not selected), the serial
data output pin is high impedance, and, if SS is low the msb (most significant bit) in the SPI data register is driven out of the serial data output
pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register takes place.
Although the SPI is capable of full-duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these
simpler devices, there is no serial data out pin
NOTE
When peripherals with full-duplex capability are used, take care not to simultaneously enable two
receivers whose serial outputs drive the same system slave’s serial data output line.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same
transmission from a master, although the master would not receive return information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched.
Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB of the SPI shifter.
If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges
cause the value previously latched from the serial data input pin to shift into the LSB of the SPI shifter.
When CPHA is set, the first edge is used to get the most significant data bit onto the serial data output pin. When CPHA is clear and the SS
input is low (slave selected), the msb of the SPI data is driven out of the serial data input pin. After the eighth shift, the transfer is considered
complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register
is set.
17.4.4 Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK)
synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave
SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line
can be used to indicate multiple-master bus contention.