Freescale Semiconductor MPC5200B 8.3 Features

MPC5200B Users Guide, Rev. 1
8-2 Freescale Semiconductor
Features
stripped along the way). Nor is the transportation of data an execution context. Without knowledge of atom boundaries and significance (if
any), the following convention is the de facto standard:
•“Bit significance, byte address”: From every observation point in a system, the relative address order of bytes shall be maintained,
and the relative significance of bits within each individual byte shall be maintained, as if they represented an 8 bit unsigned binary
integer. This is the implicit arithmetic context of bytes. The “native” bit numbering and address significance order of different
observers shall have no bearing on the byte address or bit significance order of visible data.
Byte “swapping”, the intentional transposition of bytes’ relative addresses between a source and a destination to maintain inter-byte
significance, is improper.
Bit “swizzling”, the intentional renumbering of bit positions, is perfectly legal if necessary to maintain intra-byte bit significance
or inter-byte address order. When necessary, it is required; when not necessary, it is prohibited.
To correctly join data path segments in accordance with this convention, the bit significance and byte addressing of each segment must be
specified.
In this document, significance is always msb on the left, lsb on the right, if any significance relationship exists.
All multi-bit components of the internal XL bus are defined with bit numbers and byte addresses (if any) ascending from left to right:
XLA[0:31], XLD[0:63]. The address of byte XLD[0:7] is a modulo 8 boundary, 8n (0x00, 0x08, 0x10, 0x18); the address of byte XLD[56:63]
is a modulo 8 boundary plus offset 7, 8n+7 (0x07, 0x0F, 0x17, 0x1F).
All internal IP busses are defined with bit numbers descending from left to right: IPA[31:0], IPD[31:0]. The byte addresses of IPD[31:0] are
defined acsending from left to right: IPD[31:24] is a modulo 4 address boundary, 4n (0x00, 0x04, 0x08, 0x0C); IPD[7:0] is a modulo 4 address
boundary plus offset 3, 4n+3 (0x03, 0x07, 0x0B, 0x0F). IPA[31:0] correspond left-to-right with XLA[0:31]. IPD[31:0] correspond
left-to-right with XLD[0:31] (XLA[29] == 0) or XLD[32:63] (XLA[29] == 1).
The Memory Controller registers are defined with byte addresses and bus bit numbers ascending from left to right; but object bit fields within
the registers may have ascending or descending bit numbers. The numbering order of bits as a bus does not govern the numbering order of
bits within a data object.
All external memory interface busses are defined with descending bit numbers: MEM_MA[12:0], MEM_MBA[1:0], MEM_MDQ[31:0],
MEM_DQM[3:0], MEM_MDQS[3:0]. Byte addressing of MEM_MDQ[31:0], MEM_DQM[3:0], and MEM_MDQS[3:0] is ascending:
MEM_MDQ[31:24], MEM_DQM[3], and MEM_MDQS[3] are associated with address offset 0 modulo 4 (4n); MEM_MDQ[7:0],
MEM_DQM[0], and MEM_MDQS[0] are associated with address offset 3 modulo 4 (4n+3).
8.3 Features
The MPC5200B SDRAM Memory Controller has the following features:
• Supports either:
— SDR SDRAM—memory I/Os are powered at 3.3V
— DDR SDRAM—memory I/Os are powered at 2.5V
DDR SDRAM transfers data at twice the rate and uses MEM_CLK and MEM_CLK as a differential pair.
• 32-bit memory data bus
• 16-bit memory data bus (connected only to upper half, bits 31-16, of the data bus).
• Maximum address space 512MB; 256MB per CS, 32-bit memory data bus:
— Up to 13 bits of row address (RA[12:0])
— Up to 12 bits of column address (CA[11:0])
— 2 bits of bank address (BA[1:0])
— Cannot use all 13 bits of RA and all 12 bits of CA at the same time. Maximum total address bits (RA+CA+BA) ≤ 26; 26 address
bits x 4Byte data bus = 256MB.
NOTE
In this document the Auto Precharge control signal (A10 usually), conveyed on the memory address
bus along with column address, is never included in the stated CA width; it is always in addition to
the CA width.
The Memory Controller does not support memory devices with >8 CA bits, but <13 RA bits.
RA[12:0] correspond directly with MEM_MA[12:0]. CA[7:0] correspond directly with
MEM_MA[7:0]. CA[11:8] do not correspond directly with MEM_MA[12:8].
• Maximum address space 512MB; 256MB per CS, 16-bit memory data bus:
— Up to 13 bits of row address (RA[12:0])
— Up to 13 bits of column address (CA[12:0])