MPC5200B Users Guide, Rev. 1
8-18 Freescale Semiconductor
Functional Description
Some of the configuration parameters required by the memory are also needed by the Memory Controller for command generation. The
parameters are:
• burst length
• latency
These must be programmed in the Memory Controller Configuration registers separately from setting the memory Mode register.
8.4.4.2 Precharge All Banks Command
The Memory Controller issues the Precharge command only when necessary for one of the following conditions:
• Access to a new row
• Refresh interval elapsed
• Software commanded Precharge
NOTE
DRAMs also have a maximum bank open period, after which a precharge is required. The Memory
Controller does not time the bank open period because the refresh interval is always less.
The Precharge command puts SDRAM into an idle state. In this state, the following commands can be issued:
• Refresh
• Bank Active
• Load Mode/Extended Mode Register
NOTE
The Memory Controller does not support the Precharge Selected Bank memory command.
8.4.4.3 Row and Bank Active Command
SDRAM devices have 4 internal banks. A particular row and bank of memory must be activated to allow read and write accesses. For page
mode support, the Memory Controller keeps the active row and bank(s) open as long as possible.
In an SDRAM device each internal bank can have one active row. The Bank Active command activates a row of one bank. The Memory
Controller only supports the same active row in all banks of each CS space independently. The page size of a CS space is equal to the space
size divided by the number of rows; but the page may not be contiguous in the XLB address space because the XLA bits for memory column
address bits [11:8] and memory column address [7:0] are not consecutive. The size of a contiguous page segment is 4KB, corresponding to 8
CA bits plus 2 BA bits times 4Bytes of data.
Each CS space almost always has an active row. If no row is already active, any read or write access will activate one; and the only reasons
that a row is deactivated are to activate a different one instead, or to perform a refresh.
8.4.4.4 Read Command
When the Memory Controller receives a read request via the XL bus, it first checks the row and bank of the new access. If the address falls
within the active row of an active bank, it is a page hit, and the Read command is issued as soon as possible (pending any delays required by
previous commands). If the address is within the active row, but the needed bank is inactive, or if there is no active row, the Memory Controller
will issue a Bank Active command followed by the Read command. If the address is not within the active row, the Memory Controller will
issue a Precharge command to close the active row, followed by a Bank Active command to activate the necessary bank and row for the new
access, followed finally by the Read command.
The Precharge and Bank Active commands (if necessary) can sometimes be issued in parallel with an on-going data movement.
All Reads, whether Burst or Single, must be allowed to complete the entire burst length on the memory bus. With SDR memory, the Data
Masks are negated throughout the entire Read burst length. With DDR memory, the Data Masks are asserted throughout the entire Read burst
length; but DDR memory ignores the Data Masks during Reads.
8.4.4.5 Write Command
When the Memory Controller receives a write request via the XL bus, it first checks the row and bank of the new access. If the address falls
within the active row of an active bank, it is a page hit, and the Write command is issued as soon as possible (pending any delays required by
previous commands). If the address is within the active row but the needed bank is inactive, or if there is no active row, the Memory Controller
will issue a Bank Active command followed by the Write command. If the address is not within the active row, the Memory Controller will
issue a Precharge command to close the active row, followed by a Bank Active command to activate the necessary row and bank for the new
access, followed finally by the Write command.
The Precharge and Bank Active commands (if necessary) can sometimes be issued in parallel with an on-going data movement.