Table of Contents
Paragraph Pa ge
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-3
Chapter 7 System Integration Unit (SIU)
7.1 Overview ............................................................................ .......................................................................................7-1
7.2 Interrupt Controller ............................................................... .................................................................................. ...7-1
7.2.1 Block Description .......................................................................... .....................................................................7-1
7.2.1.1 Machine Check Pin—core_mcp ............................ ....................................................................................... 7-2
7.2.1.2 System Management Interrupt—core_smi ......................... ..........................................................................7-2
7.2.1.3 Standard Interrupt—core_int ..................................... ...................................................................................7-2
7.2.2 Interface Description ......................................... ...................................................................................... ............7-4
7.2.3 Programming Note ............................................ .................................................................................... ..............7-4
7.2.4 Interrupt Controller Registers .................................................................................. ...........................................7-5
7.2.4.1 ICTL Peripheral Interrupt Mask Register—MBAR + 0x0500 .....................................................................7-5
7.2.4.2 ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504 ..............................................7-7
7.2.4.3 ICTL Peripheral Priority and HI/LO Select 2 Register —MBAR + 0x0508 ..............................................7-8
7.2.4.4 ICTL Peripheral Priority and HI/LO Select 3 Register —MBAR + 0x050C ..............................................7-8
7.2.4.5 ICTL External Enable and External Types Register —MBAR + 0x0510 ...................................................7-9
7.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register—MBAR + 0x0514 ..........................................7-10
7.2.4.7 ICTL Main Interrupt Priority and INT/SMI Select 1 Register —MBAR + 0x0518 .................................7-12
7.2.4.8 ICTL Main Interrupt Priority and INT/SMI Select 2 Register—MBAR + 0x051C ........... .......................7-13
7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR + 0x0524 ..................................7-14
7.2.4.10 ICTL Critical Interrupt Status All Register—MBAR + 0x0528 ................................................................7-15
7.2.4.11 ICTL Main Interrupt Status All Register—MBAR + 0x052C ...................................................................7-16
7.2.4.12 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530 ............................................................7-17
7.2.4.13 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538 ............................................................7-18
7.2.4.14 ICTL Main Interrupt Emulation All Register—MBAR + 0x0540 .............................................................7-19
7.2.4.15 ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544 .....................................................7-20
7.2.4.16 ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 ............................ ..................................7-21
7.3 General Purpose I/O ( GPIO) ..................................................................................... .............................................7-21
7.3.1 GPIO Pin Multiplexing ....................... ......................................................................................... .....................7-24
7.3.1.1 PSC1 (UART1/ AC97/CODEC1 ) ........ ....................................................................................... ..............7-25
7.3.1.2 PSC2 (CAN1/2/UART2/ AC97/CODEC2 ) .................................................................... ...........................7-25
7.3.1.3 PSC3 (USB2/ CODEC3/SPI /UART3) .................... .................................................................................7-25
7.3.1.4 USB1/RST_CONFIG .............................................. ...................................................................................7-25
7.3.1.5 Ethernet/USB2 /UART4/5/J1850/RST_CONFIG .....................................................................................7-25
7.3.1.6 PSC6 ............................................................................ ...............................................................................7-26
7.3.1.7 I2C ............................................................................ ...................................................................................7-26
7.3.1.8 GPIO Timer Pins ............... ......................................................................................... ................................7-26
7.3.1.9 Dedicated GPIO Port ............................. ..................................................................................... ................7-27
7.3.2 GPIO Programmer’s Model .................................. ....................................................................................... .....7-27
7.3.2.1 GPIO Standard Registers—MBAR+0x0B00 ...................... ......................................................................7-27
7.3.2.1.1 GPS Port Configuration Register—MBAR + 0x0B00 ........................................................................7-2 8
7.3.2.1.2 GPS Simple GPIO Enables Register—MBAR + 0x0B04 ...................................................................7-31
7.3.2.1.3 GPS Simple GPIO Open Drain Type Register —MBAR + 0x0B08 ...................................................7-32
7.3.2.1.4 GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C .......................................................7-33
7.3.2.1.5 GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10 ...............................................7-36
7.3.2.1.6 GPS Simple GPIO Data Input Values Register —MBAR + 0x0B14 ..................................................7-37
7.3.2.1.7 GPS GPIO Output-Only Enables Register —MBAR + 0x0B18 .............. ...........................................7-38
7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register —MBAR + 0x0B1C ............ ................................7-39
7.3.2.1.9 GPS GPIO Simple Interrupt Enable Register—MBAR + 0x0B20 ......................................................7-40
7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24 ...........................7-40
7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register —MBAR + 0x0B28 ........................................7-41
7.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register —MBAR + 0x0B2C ......................................7-42
7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30 ......................................7-42
7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34 ......................... ..............7-43
7.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38 .........................................7-44