Freescale Semiconductor MPC5200B Chapter 21 Debug Support and JTAG Interface, Appendix A Acronyms and Terms Appendix B List of Registers

Table Of C onte nts
Paragraph Pa ge
Number Number
MPC5200B Users Guide, Rev. 1
TOC-18 Freescale Semiconductor
20.8.8.1 Transmitting Or Receiving A Block Mode Message ...............................................................................20-45
20.8.8.2 Transmitting Or Receiving A Message In 4X Mode ............................................................. ...................20-46
20.8.9 BDLC Module Initialization ................................................................................................................ ..........20-47
20.8.9.1 Initialization Sequence .................................................................. ...........................................................20-47
20.8.9.2 Initializing the Configuration Bits ....................... ..................................................................................... 20-48
20.8.9.3 Exiting Loopback Mode and Enabling the BDLC module ........................... ...........................................20-48
20.8.9.4 Enabling BDLC Interrupts .................................................................. ......................................................20-48
20.9 Resets ....................................................................... ...................................................................................... ........20-50
20.9.1 General ....................................................................... .....................................................................................20-50
Chapter 21 Debug Support and JTAG Interface
21.1 Overview ............................................................................ .....................................................................................21-1
21.2 TAP Link Module (TLM) and Slave TAP Implementation ....................................................................................21-1
21.3 TLM and TAP Signal Descriptions .......................................... ...............................................................................21-4
21.3.1 Test Reset (TRST) ......................................................................... ...................................................................21-4
21.3.2 Test Clock (TCK) ..................................................................... ........................................................................21-4
21.3.3 Test Mode Select (TMS) ........................................... ...................................................................................... .21-4
21.3.4 Test Data In (TDI) ......................................................................... ...................................................................21-4
21.3.5 Test Data Out (TDO) .... ......................................................................................... ...........................................21-5
21.4 Slave Test Reset (STRST) ................................................... ...................................................................................21-5
21.4.1 Enable Slave—ENA[0 :n] ................................................. ...............................................................................21-5
21.4.2 Select DR Link—SEL[0 :n] ............................................................................................................................. 21-5
21.4.3 Slave Test Data Out—STDO[0 :n] .................... ......................................................................................... .....21-5
21.5 TAP State Machines ......................... ..................................................................................... ..................................21-5
21.6 G2_LE Core JTAG/COP Serial Interface ................................................................................. ..............................21-6
21.7 TLM Link DR Instructions ..................................................................... .................................................................21-7
21.7.1 TLM:TLMENA .......... ........................................................................................................... ...........................21-8
21.7.2 TLM:PPCENA ............. ....................................................................................................................................21-8
21.8 TLM Test Instructions .......................................... ....................................................................................... ............21-8
21.8.1 IDCODE ........................................................................ ...................................................................................21-8
21.8.1.1 Device ID Register ................................................................................... ..................................................21-8
21.8.2 BYPASS ........................................................................ ...................................................................................21-8
21.8.3 SAMPLE/PRELOAD ............ .............................................................................................. .............................21-8
21.8.4 EXTEST ......................................................................... ...................................................................................21-9
21.8.5 CLAMP ........................................................................ .....................................................................................21-9
21.8.6 HIGHZ ........................................................................... ...................................................................................21-9
21.9 G2_LE COP/BDM Interface .................... ................................................................................... ...........................21-9
Appendix A Acronyms and Terms
Appendix B List of Registers