Freescale Semiconductor MPC5200B 20.8.3 Protocol Handler, 4-Bit Up/Down Counter up/down out dq, Input Sync dq

MPC5200B Users Guide, Rev. 1
20-28 Freescale Semiconductor
Functional Description
Figure 20-11. BDLC Module Rx Digital Filter Block Diagram
• Operation
The clock for the digital filter is provided by the MUX Interface clock.At each positive edge of the clock signal, the current state of
the Receiver input signal from the RXB pad is sampled.The RXB signal state is used to determine whether the counter should
increment or decrement at the next positive edge of the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample is low.The counter will thus progress
up towards ‘15’ if, on average, the RXB signal remains high or progress down towards ‘0’ if, on average, the RXB signal remains
low.
When the counter eventually reaches the value ‘15’, the digital filter decides that the condition of the RXB signal is at a stable logic
level one and the Data Latch is set, causing the Filtered Rx Data signal to become a logic level one. Furthermore, the counter is
prevented from overflowing and can only be decremented from this state.
Alternatively, should the counter eventually reach the value ‘0’, the digital filter decides that the condition of the RXB signal is at
a stable logic level zero and the Data Latch is reset, causing the Filtered Rx Data signal to become a logic level zero. Furthermore,
the counter is prevented from underflowing and can only be incremented from this state.
The Data Latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the RXB
signal.
• Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the RXB signal transitions, then there will be a delay before that transition appears at the Filtered Rx Data output
signal. This delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling
points. This ‘filter delay’ must be taken into account when performing message arbitration.
For example, if the frequency of the MUX Interface clock (fbdlc) is 1.0486MHz, then the period (tbdlc) is 954ns and the maximum
filter delay in the absence of noise will be 15.259us.
The effect of random noise on the RXB signal depends on the characteristics of the noise itself. Narrow noise pulses on the RXB
signal will be completely ignored if they are shorter than the filter delay. This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition may be delayed by an amount equal to the length of the
noise burst. This is just a reflection of the uncertainty of where the transition is truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length will be detected by the next
stage of the BDLC module’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length will normally be detected as an invalid symbol or as invalid
data when the frame’s CRC is checked.
20.8.3 Protocol Handler
The Protocol Handler is responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The Protocol
Handler conforms to SAE J1850 - Class B Data Communications Network Interface. Refer to Figure 20-2
4-Bit Up/Down Counter
up/down out dq
Filtered
Rx Data Out
MUX Interface Clock
Input
Sync
dq
Rx Data
from
RXB pad
4Edge &
Count
Comparator